參數(shù)資料
型號(hào): AND8009
廠商: ON SEMICONDUCTOR
英文描述: ECLinPS Plus SPICE Modeling Kit
中文描述: 業(yè)界的EClinPS加SPICE建模套件
文件頁(yè)數(shù): 32/67頁(yè)
文件大?。?/td> 211K
代理商: AND8009
AND8009/D
http://onsemi.com
32
Package: TSSOP20
* SPICE subcircuit file of coupled transmission lines
*
* Transmission line model
*
* Conductor numberpin designation cross reference:
* Conductor Pin
* 1 1
* 2 2
* 3 3
* 4 4
* 5 5
* 6 6
* 7 7
* 8 8
* 9 9
* 10 10
* 11 11
* 12 12
* 13 13
* 14 14
* 15 15
* 16 16
* 17 17
* 18 18
* 19 19
* 20 20
*
* number of lumps: 1
* FASTEST APPLICABLE EDGE RATE: 0.114 ns
* Equivalent bandwidth: 3.07GHz
* COMPRESSION OF SUBCIRCUITS PERFORMED: discard ratio is 0.050
*
**CONNECT CHIP SIDE TO N**I AND BOARD SIDE TO N**O
* ECLinPS PLUS usage requires the input nodes used in the subcircuit call
* statement(X_777) that are tied to global ports(VCC, VCCO, and VEE internal
* to the die) to have the same global names in the subcircuit call statement(X_777) .
* For example, if VCC is wirebonded to pin 20 for a certain design, then N20I
* should be relabeled to VCC. Again, the change needs only to be incorporated
* in the X_777 subcircuit callout statement. Since this requires a change to
* the netlist below, it is necessary for each design to have a copy of this file with
* the appropriate changes made that are required for that design.
*
R_SHORT 0 GND 0.0001
X_777 N01I N01O N02I N02O N03I N03O N04I N04O
+ N05I N05O N06I N06O N07I N07O N08I N08O N09I N09O
+ N10I N10O N11I N11O N12I N12O N13I N13O N14I N14O
+ N15I N15O N16I N16O N17I N17O N18I N18O N19I N19O
+ N20I N20O GND PACKAGE
.SUBCKT PACKAGE N01I N01O N02I N02O N03I N03O N04I N04O
+ N05I N05O N06I N06O N07I N07O N08I N08O N09I N09O
+ N10I N10O N11I N11O N12I N12O N13I N13O N14I N14O
+ N15I N15O N16I N16O N17I N17O N18I N18O N19I N19O
+ N20I N20O GND
R01WB N01I N01W 5.225e02
L01WB N01W N01R 1.254e09
R01 N01R N01C 2.100e03
C01 N01C GND 1.840e13
L01 N01C N01O 1.603e09
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