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AND8009/D
http://onsemi.com
3
SPICE Netlists
The netlists are organized as a group of subcircuits. In
each subcircuit model netlist, the model name is followed by
a list of external node interconnects.
Temperature Compensation Network for 100EP
The output netlists include temperature compensation
network circuitry for 100EP style output buffers. The circuit
components of the temperature compensation networks are
shown in Figure 18. For simulating 10EP style outputs these
components should either be deleted or commented out of
the subcircuit netlists. Subcircuit models such as the Input
or Output Buffer, Package, Input ESD and Output ESD
should connect to supplies through hierarchical, passed
parameters such as V
CC
, V
EE
, etc., for proper simulation and
not separately attached to independent power supplies.
SPICE Parameter Information
In addition to the schematics and netlists is a listing of the
SPICE parameters for the transistors referenced in the
schematics and netlists. These parameters represent a typical
device of a given transistor. Varying the typical parameters
will affect the DC and AC performance of the structures; but
for the type of modeling intended by this note, the actual delay
times are not necessary and are not modeled, as a result
variation of the device parameters are meaningless. The
performance levels are more easily varied by other methods
and will be discussed in the next section. The resistors
referenced in the schematics are polysilicon and have no
parasitic capacitance in the real circuit and none is required
in the model. The schematics display the only devices needed
in the SPICE netlists.
Modeling Information
The bias drivers for the devices are not detailed since their
circuitry would result in a substantial increase of model
complexity and simulation time. Instead, these internal
reference voltages (V
BB
, V
CS
, V
HSTL
, etc.) should be driven
with ideal constant voltage sources.
The schematics and SPICE parameters will provide a
typical output waveshape, which can be seen in Figures 18,
19, and 20. Simple adjustments can be made to the models
allowing output characteristics to simulate conditions at or
near the corners of the data book specifications. Consistent
crosspoint voltages need to be maintained.
To adjust rise and fall times:
Produce the desired rise and fall times output slew rates
by adjusting collector load resistors to change the gates
tail current. The V
CS
voltage will affect the tail current
in the output differential, which will interact with the
load resistor and collector resistor to determine t
r
and t
f
at the output.
To adjust the V
OH
:
Adjust the V
OH
and V
OL
level by the same amount by
varying V
CC
. The output levels will follow changes in
V
CC
at a 1:1 ratio.
To adjust the V
OL
only:
Adjust the V
OL
level independently of the V
OH
level by
increasing or decreasing the collector load resistance.
Note that the VOH level will also change slightly due to
a I
BASE
R drop across the collector load resistor. V
OL
can
be changed by varying the VCS supply, and therefore the
gate current through the current source resistor.
Summary
The information included in this kit provides adequate
information to run a SPICE level system interconnect
simulation. Device input or output models are presented in
Table 4. For EP and LVEP series devices not listed in Table 4,
consult www.onsemi.com (Tech Support).