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參數(shù)資料
| 型號： | AN460 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Using the P82B96 for bus interface |
| 中文描述： | 使用總線接口P82B96 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 66K |
| 代理商： | AN460 |
Philips Semiconductors
Application note
AN460
Using the P82B96 for bus interface
2001 Feb 14
7
Treatment of (unused) I/O pins
In some systems, one or other side of the P82B96 might be required
to be ‘hot plugged’ to the I
2
C bus of some other separate equipment.
This will require some pull up capability
to be provided on both sides
of the plug.
Each input pin (Sx or Rx) is a high impedance input and cannot be
left floating. Internal pull-ups have not been used because they
would only pull-up to the IC supply (V
CC
), thereby demanding that
V
CC
cannot be lower than the connected bus voltages. In the
P82B96 any input may be pulled up to +15 V, independent of V
CC
.
No currents will flow into the I/O pins (except when outputs drive a
bus low). The inputs are like LM324 inputs, based on PNP input
transistors, so they source tiny currents when externally driven low.
External pull up resistors fitted at Sx pins should cause the specified
minimum 200
μ
A to flow when that input is low.
The Rx input should be treated just like any op-amp input and not
left floating. A pull-up of 100 K should cope with PCB leakage in
humid conditions.
Diodes have not been fitted between I/O pins and V
CC
, to allow
them to be pulled to voltages above the chip’s V
CC
. This permits, for
example, use of the P82B96 on a 3 V supply, driving a 3 V buffered
bus, to interface with a normal 5 V I
2
C input. It also allows the I
2
C
busses to remain active even if the P82B96 V
CC
fails.
Failure of V
CC
and consequences for bus
operation
The P82B96 maintains its function for V
CC
below 2 V. At normal
temperatures it starts to shut off at around 1.2 V. That means that if
the normal V
CC
supply is 5 V, and that supply was to fall to 2 V, then
it just retains normal operation — it cannot
‘
release’ the busses even
though the supply is now only 40% of normal.
During failure of the V
CC
power supply no abnormal signals are
caused on any I/O until the supply falls below a value below which
point there will be no signals transmitted through the chip, and all
I/Os will become open circuit. That voltage is of the order of 1 V.
Margins on switching levels
There are certain constraints that determine the two low levels on
the I
2
C bus interface Sx and Sy. The I
2
C bus must always be driven
below the lowest level that guarantees a low on any bus to which it
is connected.
For a normal 5 V I
2
C bus the minimum low is 1.5 V. The P82B96
guaranteed low level is set
well below this, at 1V maximum for the
I
2
C maximum allowed 3 mA. (It assumes a normal 5 V I
2
C bus on
the Sx/Sy side of the buffer, but this should not be taken as a
restriction)
The externally connected I
2
C chips must, in turn, pull the I
2
C pin
below the threshold required to set Tx/Ty low.
Those external chips all have a maximum static low specification of
0.4 V at 3 mA. Therefore the typical threshold for the Sx and Sy
inputs is 650 mV at 25
°
C, with 600 mV as the minimum.
If there was not a difference between the Sx low output (the larger
voltage) at the smallest permitted load current, and the Sx input
threshold (a lesser voltage) the chip would latch.
As the Sx sink current decreases the output low level at Sx decreases.
For this reason a minimum sink current at Sx is specified (200
μ
A)
The temperature coefficient on the input and output thresholds of Sx
and Sy is –2 mV/K.
The other side (Tx/Rx and Ty/Ry) is designed for connection to any
bus from 2 V to 15 V.
The typical threshold switching level is 50% of V
CC
. Tolerances
tighter than the normal 70/30% levels have been specified so the
guaranteed noise margins, especially
when working with long 15V
busses, are improved.
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