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參數(shù)資料
| 型號： | AN460 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Using the P82B96 for bus interface |
| 中文描述： | 使用總線接口P82B96 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 66K |
| 代理商： | AN460 |
Philips Semiconductors
Application note
AN460
Using the P82B96 for bus interface
2001 Feb 14
5
+5 V
1/2 P82B96
SU01020
SDA
Rx
Tx
1K
15 V
+V
CC
= 15 V
+5 V
1/2 P82B96
SDA
Rx
Tx
1K
15 V
+V
CC
= 15 V
LONG TWISTED PAIR
NOTE
: Schottky diode and zener clamps applied to limit spurious signals
Figure 7.
Driving a high voltage, low impedance “I
2
C” bus
Power dissipation under fault conditions
The current drive capability of the buffered Tx and Ty outputs
exceeds 100 mA. If a wiring fault causes a short from these pins to
V
CC
(or to a buffered bus supply when using different supplies) then
high dissipations result when Sx or Sy are driven low. The rated 300
mW dissipation can be exceeded within a very short time.
Appropriate precautions should be taken to ensure that such a
short-circuit does not occur.
Bus characteristics and rise/fall times
In general terms, the rise times which will be observed on a bus
driven by the P82B96 will be simply determined by the pull-up
resistor used and the total capacitive load presented to the bus.
The fall time is determined mostly by the dynamic pull down current
capability and the capacitive load, with some modification caused by
the varying current in the bus pull up resistor.
The effective logic signal propagation time will depend on the input
logic thresholds of the P82B96, and of any other devices connected
to the I
2
C or buffered bus.
On a 2 V supply, the Sx and Sy thresholds are approaching half the
supply rail. On a 5V
supply their (0.65V) threshold is much closer to
GND than usual for logic inputs. This causes some additional delay
in the effective propagation time on falling edges, and reduces those
delays on the rising edges.
For Rx and Ry, the threshold is always 50% of V
CC
so switching
levels are ‘conventional’ when the buffered bus pull-ups are
connected to V
CC
. However, if the buffered bus pull-ups connect to a
supply voltage different to V
CC
, the rise/fall times required to reach
the Rx threshold may need to be taken into account.
P82B96 response time for propagation of low to
high at Sx
With Tx connected to Rx, a low at Sx causes a low at Tx and thus to
Rx. The low at Rx enables a ‘clamp’ at 1V, the logic low, on Sx.
So when the Sx input is released, the voltage on the I
2
C bus rises
towards this 1V clamping level set by the return signal from Rx,
which is still low.
As Sx rises past its 0.65V input threshold, the Tx output drive will be
released. The Tx output voltage will begin to rise at a rate determined
by its load capacitance and the pull up resistor used at Tx.
With Tx connected to Rx, when it reaches 50% of the V
CC
supply
voltage the Rx input senses that Tx has been released, and returns
a ‘high’ signal to its output at Sx, allowing this voltage to continue its
rise again towards the I
2
C supply. It will be recognized as high by
other I
2
C chips when it reaches their logic threshold. Typical
waveforms are shown in Figure 8.
This delay in termination of the low signal on Sx will be further
extended if Tx and Rx are not directly linked and there are other
delays inherent in the signal path between Tx and Rx. Including slow
opto-couplers
in the loop will exaggerate these delays (see Figure 4).
Horiz: 200ns/div.
VertL 2V/div.
Sx
ch1: freq = 624 kHz
SU01071
Rx/Tx
Figure 8.
Sx = 5V I
2
C bus, Tx = buffered bus with pull-up to V
CC
= 10V
Low to High propagation of Sx with Tx linked to RX
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