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參數(shù)資料
| 型號(hào)： | AN460 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Using the P82B96 for bus interface |
| 中文描述： | 使用總線接口P82B96 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 66K |
| 代理商： | AN460 |
Philips Semiconductors
Application note
AN460
Using the P82B96 for bus interface
2
2001 Feb 14
The P82B96 offers many different ways in which it can be used as a
bus interface. In its simplest application it can be used as an
interface between bus systems operating from different supply
voltages. Opto isolation between two bus systems is possible, and
also the availability of the Tx and Rx signals permits interfacing of
the P82B96 with other bus systems which separate the forward
output path, from the backward input signal path.
The fixed, low, logic levels used at Sx imply a restriction that the I
2
C
bus connection on this chip should be used only with small I
2
C
systems, contained typically on one printed circuit board, and not
connected with long wiring which could introduce noise.
It is the intention that the P82B96 be used as an interface to long or
noisy bus systems so that the function of each local I
2
C bus node
remains within specification, and the P82B96 handles the more
difficult interfacing tasks.
Series resistors in the SDA/SCL lines should also be avoided in the
Sx lines at I
2
C nodes that include P82B96.
A further implication of the way in which the P82B96 functions is that
if two P82B96 chips have their Sx pins connected to the same I
2
C
node, then signals from the Rx input of one P82B96 will not
propagate to Tx on the other. This is dictated by the non-latching
requirement that they must not propagate back to Tx within one
chip.
As the buffered output of the P82B96 has increased drive capability
over the normal I
2
C specification, these limitations do not present
any great restriction. The buffered side can be used for
interconnection, and distance.
There are also some issues which need to be considered in
protecting the P82B96 from spurious signals in a bus line installed
over a long distance, or where signals may be picked up which
exceed the supply rail levels.
INTERFACING DIFFERENT SUPPLY/LOGIC
LEVELS
Figure 1 shows P82B96 applied with the I/O pins Tx and Rx linked
to provide a new bus with the same protocol and properties as I
2
C
but operating at different logic levels. Because Tx has an open
collector output a pull-up resistor is applied.
Supply voltages in the range 2 V to 15 V are permitted, allowing
interfacing from a conventional 5 V I
2
C bus to 3 V logic systems or
low current bus systems such as SMB with 350
μ
A pull-down
current. It must be remembered that the input threshold at Rx on the
buffered bus side is nominally at one half of the V
CC
voltage.
Hence longer cable runs and ground potential differences can be
accommodated by using a 15 V supply to improve noise immunity
while retaining the simplicity of I
2
C wiring.
The oscilloscope traces, Figures 2 and 3, show the waveforms at
Tx, Rx, and Sx when Tx is not linked to Rx. Tx has a 330
pull-up to
the chip supply of 10 V, Sx has a 1600
pull-up to a 5 V supply.
There is no external capacitive bus loading. The propagation delay
for signals from Sx to Tx is about 100ns, and from Rx to Sx it is
about 300ns.
I
2
C
SDA
+5 V
+V
CC
(2–15 V)
R1
‘SDA’
(NEW LEVELS)
1/2 PB2B96
Rx
(SDA)
Tx
(SDA)
SU01021
NOTE
: The logic voltages and currents at ‘SDA’ are set by V
CC
and pull-up.
EXAMPLE
: ‘SMB’ bus l
low
= 350 A, use V
CC
= 5 V and pull-up R1 = 13 K
Figure 1.
Interfacing an “I
2
C” type of bus with different logic levels
Horiz: 200ns/div.
VertL 2V/div.
10V
5V
0V
Tx
Sx
ch1: freq = 624 kHz
SU01069
CH1!2.00V = AVG
CH2!2.00V = BWL MTB 200ns – 0.98dvch1+
Figure 2.
Sx pull-up to 5V, Tx pull-up to V
CC
= 10V
Propagation Sx to Tx
Horiz: 200ns/div.
VertL 2V/div.
Sx
ch1: freq = 624 kHz
SU01070
CH1!2.00V = AVG
CH2!2.00V = BWL MTB 200ns – 0.98dvch1+
Rx
Figure 3.
Sx pull-up to 5V, V
CC
= 10V
Propagation Rx to Sx
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