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參數(shù)資料
| 型號： | AN2546FH-A |
| 廠商： | PANASONIC CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SOCKET FULL LID LCC 68 POS GOLD |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 25/30頁 |
| 文件大?。?/td> | 520K |
| 代理商： | AN2546FH-A |
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AN2546FH-A
25
SDB00081BEB
■
Technical Data (continued)
1. Serial interface description (continued)
2) Mode setting channel bits table (continued)
(5) ch.18: PLL stop position and vertical sync. position adjustment (continued)
<Vertical synchronous output timing adjustment range>
Pin 35 input
Composite sync.
signal odd number
field
Pin 31 output
odd number field
FIXHD
=
"0"
Pin 31 output
odd number field
FIXHD
=
"1"
8H
2H to 9H (D0 to D2)
3Η
Composite sync.
signal even number
field
Pin 31 output
EXCHF
=
"1"
FIXHD
=
"0"
Pin 31 output
EXCHF
=
"1"
FIXHD
=
"1"
Pin 31 output
EXCHF
=
"0"
FIXHD
=
"0"
Pin31 output
EXCHF
=
"0"
FIXHD
=
"1"
8H
8H
3Η
3Η
The above timing chart indicates (D2,D1,D0)
=
"101".
For (D2,D1,D0)
=
"000", the pin 32 output width is 9H.
The pin 31 timing is synchronous with the pin 35 input timing. The above timing chart is just for reference
1.5H to 8.5H (D0 to D2)
2.5H to 9.5H (D0 to D2)
Pin 35 input
Composite sync.
signal odd number
field
Odd number field
EXCHF
=
"1"
EXCHF
=
"0"
Composite sync.
signal even number
field
6H to 9H (D3 to D4)
Horizontal PLL on
Horizontal PLL off
0-line
1
2
3
5.5H to 8.5H (D3 to D4)
Horizontal PLL on
Horizontal PLL off
6.5H to 9.5H (D3 to D4)
Horizontal PLL on
Horizontal PLL off
The above timing chart indicates (D4,D3)
=
"01".
PLL stop line number:254-line (NTSC)
302-line (PAL)
<Horizontal PLL start position adjustment range>
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