參數(shù)資料
型號： AN2546FH-A
廠商： PANASONIC CORP
元件分類： 消費(fèi)家電
英文描述： SOCKET FULL LID LCC 68 POS GOLD
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, PLASTIC, QFP-64
文件頁數(shù)： 22/30頁
文件大?。?/td> 520K
代理商： AN2546FH-A
AN2546FH-A
SDB00081BEB
22
■
Technical Data (continued)
1. Serial interface description (continued)
1) I
2
C bus control mode (continued)
(3) Subaddress transfer
When a data transfer mode bit is 0, all the serial data columns transferred until a stop condition is set is
regarded as the data block.
(5) Stop condition
When S-data changes from low level to high level at SCLK
=
high level, data reception is halted.
(6) Pulse timing
Timing chart expanded diagram
(4) Data transfer
Data transfer
Slave address transfer
Acknowledge bit
1
D7
D6
D5
D4
D3
D2
D1
D0
Pin 48
S-data
Pin 47
SCLK
2
3
4
5
6
7
8
9
8
9
1
2
Data transfer mode bit
"1": Data update mode
"0": Auto increment mode
Acknowledge bit
1
D7
D6
D5
D4
D3
D2
D1
D0
Pin 48
S-data
Pin 47
SCLK
2
3
4
5
6
7
8
9
8
9
1
2
At auto increment mode: Data transfer
At data update mode: Stop condition
Pin 48
S-data
Pin 47
SCLK
t
f
t
LOW
t
BUF
t
HDSTA
t
r
t
HIGH
t
SUDAT
t
SUSTO
t
HDDAT
Parameter
Symbol
Min
Typ
Max
Unit
SCLK clock frequency
t
SCL
t
BUF
t
HDSTA
t
LOW
t
HIGH
t
HDDAT
t
SUDAT
t
r
t
f
t
SUSTO
0
400
300
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
ns
Bus free-time for stop condition and start condition
1.3
Hold time start condition
0.6
SCLK clock low-state hold time
1.3
SCLK clock high-state hold time
0.6
Data hold time
0
Data setup time
100
0.6
S-data and SCLK signal rise time
ns
S-data and SCLK signal fall time
300
ns
μ
s
Stop condition setup time
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