參數(shù)資料
型號(hào)： AN2546FH-A
廠商： PANASONIC CORP
元件分類： 消費(fèi)家電
英文描述： SOCKET FULL LID LCC 68 POS GOLD
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, PLASTIC, QFP-64
文件頁(yè)數(shù)： 24/30頁(yè)
文件大?。?/td> 520K
代理商： AN2546FH-A
AN2546FH-A
SDB00081BEB
24
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Technical Data (continued)
1. Serial interface description (continued)
2) Mode setting channel bits table (continued)
(1) ch.5: Black limiter adjustment
Sub-
address
D7
D6
D5
D4
D3
D2
D1
D0
DCLP
0A
0
NAVI sync. mode (Pin 45)
1
Video sync. mode (Pin 46)
(4) ch.17: Mode setup 1
Sub-
address
D7
D6
D5
D4
D3
D2
D1
D0
11
DFVD
DFSC
DPALM
DPALN
DSECAM DVMODE
DUV
DCINT
Mode
Function
DFVD
0
VD cycle: 60 Hz
1
VD cycle: 50 Hz
DFSC
0
Subcarrier: 3.58 MHz
1
High
=
PALM mode on
High
=
PALN mode on
High
=
SECAM mode on
High
=
Burst swing off
0
Chrominance input
Subcarrier: 4.43 MHz
DPALM
DPALN
DSECAM
DVMODE
DUV
1
Color difference signal input
DCINT
0
RGB signal input
1
Video signal input
at NTSC selection
DFVD/DFSC/DPALM/DPALN/DSECAM
=
Low
DVMODE
=
High
at PAL selection
DFVD/DFSC
=
High
DPALM/DPALN/DSECAM/DVMODE
=
Low
at PALM selection
DPALM/DFVD
=
High
DPALN/DSECAM/DVMODE
=
Low
at PALN selection
DPALN
=
High
DPALM/DSECAM/DVMODE/DFVD
=
Low
(5) ch.18: PLL stop position and vertical sync. output position adjustment
Sub-
address MACRON
D7
D6
D5
D4
D3
D2
D1
D0
PLL stop position adjustment
AFC normal operation
Vertical position adjustment
12
0
1
Copy guard signal correspondence
(3) ch.10: White peak limiter adjustment
Sub-
address
D7
HGA
D6
D5
D4
D3
D2
D1
D0
05
0
Output gain down mode
1
Gain mode
(2) ch.7: Aperture adjustment
Sub-
address
D7
D6
D5
D4
D3
D2
D1
D0
DCLP
07
0
VD free-run: NTSC
=
265H, PAL
=
315H
VD free-run : NTSC
=
263H, PAL
=
313H
1
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