參數(shù)資料
型號(hào)： AN-30
英文描述： TOPSwitch-GX Forward Design Methodology
中文描述： 的TOPSwitch - GX系列正向設(shè)計(jì)方法
文件頁(yè)數(shù)： 12/40頁(yè)
文件大?。?/td> 311K
代理商： AN-30
AN-30
12
B
12/02
Estimate the power lost in the core from the manufacturer’s data
on the core material, operating frequency and B
. Copper losses
may be estimated from the resistance and RMS current in each
winding. If the estimates indicate excessive loss, repeat the
design with a larger core.
Zero Gap Transformers
For highest efficiency in this application with the simple Zener
clamp circuit, it is recommended that the transformer core have
no air gap. While an air gap reduces the remnant flux density
and stabilizes the primary inductance, it increases the stored
energy that must be processed by the clamp circuit.
With the use of a suitable reset scheme, transformer saturation
is not a problem in the absence of an air gap. Using this
methodology and the recommended clamp scheme, the design
restricts peak flux density and the clamp circuit produces
negative magnetizing current during reset.
The negative magnetizing current during reset prevents flux
build-up in the transformer during successive switching periods.
Even with no intentional gap in the transformer core, mechanical
imperfections will always give a finite effective gap (when
calculating with
PI Expert
a value of 0.02 mm is used). If an air
gap is desired for other reasons, it should be as small as possible.
Step 7. Check primary current.
Use the actual number of turns from the design of the transformer
to compute the peak and RMS current on the primary. Primary
current was estimated in Step 4 with an ideal turns ratio before
the transformer was designed. Add the peak of the magnetizing
current to obtain actual peak of the primary current under
steady-state conditions.
Designers should be aware that the primary current observed on
prototype hardware may be lower than predicted because the
circuit that resets the flux in the transformer allows a negative
average magnetizing current, as mentioned previously in
Step 6 in the section on Zero Gap Transformers. The design,
however, must allow for conditions when the magnetizing
current adds to the reflected secondary currents.
Step 8. Determine the input capacitance for holdup time.
The holdup time must be specified at a minimum voltage
V
. This is often, but not always V
. For maximum
flexibility, this methodology allows the designer to determine
the value of input capacitance required to obtain a given holdup
time from an arbitrary input voltage.
If a DC voltage is specified to mark the beginning of the holdup
time, the minimum required input capacitance is
(27)
where P
is the total output power that corresponds to the
efficiency at the DC bus,
η
DC
and t
H
is the holdup time.
If an AC voltage V
is specified to mark the beginning of
the holdup time, the minimum required input capacitance (no
doubler) is
(28)
where t
is the conduction time of the AC input rectifiers and f
L
is the frequency of the AC power line. Again, note that t
C
will
increase significantly if the design has passive PFC.
The efficiency
η
excludes losses in the AC input circuit and
EMI filter. No power is dissipated in the AC input circuit during
the holdup time because the AC input is disconnected. The
lower system efficiency
η
that includes the AC input losses
would give a value of C
IN
that is larger than required.
Compare the value from Equation (27) or (28) with the estimate
for C
in Step 1. Adjust C
in Step 1 and repeat the calculations
until the computed value is approximately the same as in
Step 1.
Step 9. Calculate stress on rectifiers.
PI Expert
calculates voltage and current stress on rectifiers for
guidance in selection of appropriate components. The
recommended derating factor for peak inverse voltage is 80%.
Derating for the currents is generally not necessary.
Thus, the recommended voltage rating for the input bridge
rectifier is
V
PIVAC
=
1 25 2
.
(29)
Current ratings for rectifiers are average values, not RMS. The
current rating for the bridge rectifier is computed from
(30)
where V
is the average DC bus voltage at the lowest steady-
state line voltage (no doubler).
(31)
C
P t
V
V
IN
DC
HOLDUP
DROPOUT
≥
(
)
2
2
2
η
V
ACMAX
I
P
V
DAVBR
O
DC
LL
=
η
C
P
t
t
f
V
V
IN
O
DC
H
C
L
ACHOLDUP
DROPOUT
≥
(
)
+
2
η
2
1
2
2
2
V
V
V
P
f
t
C
LL
ACMIN
ACMIN
O
L
C
DC
IN
=
+
η
2
2
1
2
2
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