參數(shù)資料
型號(hào)： AM79C874VC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP80
封裝： 12 X 12 MM, PLASTIC, MO-136BAM, TQFP-80
文件頁(yè)數(shù)： 29/60頁(yè)
文件大?。?/td> 869K
代理商： AM79C874VC
Am79C874
29
P R E L I M I N A R Y
Bad Management Frame Handling
The management block of the device can recognize
management frames without preambles (preamble
suppression). However, if it receives a bad manage-
ment frame, it will go into a Bad Management Frame
state. It will stay in this state and will not respond to any
management frame without preambles until a frame
with a full 32-bit preamble is received, then it will return
to normal operation.
A bad management frame is a frame that does not
comply with the IEEE standard specification. It can be
one with less than 32-bit preamble, with illegal OP field,
etc. However, a frame with more than 32 preamble bits
is considered to be a good frame.
After a reset, the NetPHY-1LP device requires a mini-
mum preamble of 32 bits before management data
(MDIO) can be received. After that, the management
data being received by the NetPHY-1LP device does
not require a preamble.
REGISTER DESCRIPTIONS
The following registers given in Table 8 are supported
(register addresses are in decimal).
Table 8.
Register Summary
The Physical Address of the PHY is set using the pins
defined as PHYAD[4:0]. These input signals are
strapped externally and sampled as when reset goes
high. The PHYAD pins can be reprogrammed via soft-
ware.
Serial Management Registers
A detailed definition of each Serial Management regis-
ter follows. The mode legend is shown in Table 9.
Table 9.
Legend for Register Table
Register
Address
(in
Decimal)
Description
0
MII Management Control Register
1
MII Management Status Register
2
PHY Identifier 1 Register
3
PHY Identifier 2 Register
4
Auto-Negotiation Advertisement Register
5
Auto-Negotiation Link Partner Ability Register
6
Auto-Negotiation Expansion Register
7
Next Page Advertisement Register
8-15
Reserved
16
Miscellaneous Features Register
17
Interrupt Control/Status Register
18
Diagnostic Register
19
Power Management & Loopback Register
20
Reserved
21
Mode Control Register
22
Reserved
23
Disconnect Counter
24
Receive Error Counter
25-31
Reserved
Type
RW
SC
LL
RO
RC
LH
Description
Readable and writable
Self Clearing
Latch Low until clear
Read Only
Cleared on the read operation
Latch high until clear
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AM79C874VD 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP
AM79C874VF 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP
AM79C874VI 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP
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