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參數(shù)資料
| 型號(hào)： | AM79C874VC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP80 |
| 封裝： | 12 X 12 MM, PLASTIC, MO-136BAM, TQFP-80 |
| 文件頁數(shù)： | 28/60頁 |
| 文件大?。?/td> | 869K |
| 代理商： | AM79C874VC |
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28
Am79C874
P R E L I M I N A R Y
PHY CONTROL AND MANAGEMENT
BLOCK (PCM BLOCK)
Register Administration for 100BASE-X
PHY Device
The management interface specified in Clause 22 of
the IEEE 802.3u standard provides for a simple two
wire, serial interface to connect a management entity
and a managed PHY for the purpose of controlling the
PHY and gathering status information. The two lines
are Management Data Input/Output (MDIO), and Man-
agement Data Clock (MDC). A station management
entity which is attached to multiple PHY entities must
have prior knowledge of the appropriate PHY address
for each PHY entity.
Description of the Methodology
The management interface physically transports man-
agement information across the MII. The information is
encapsulated in a frame format as specified in Clause
22 of IEEE 802.3u draft standard and is shown in
Table 6.
Table 6.
Clause 22 Management Frame Format
The PHYAD field, which is five bits wide, allows 32
unique PHY addresses. The managed PHY layer de-
vice that is connected to a station management entity
via the MII interface has to respond to transactions
addressed to the PHY address. A station management
entity attached to multiple PHYs, such as in a managed
802.3 Repeater or Ethernet switch, is required to have
prior knowledge of the appropriate PHY address. See
Table 7 and Figure 7.
Table 7.
PHY Address Setting Frame Structure
Figure 7.
PHY Management Read and Write Operations
PRE
1.1
1.1
ST
01
01
OP
10
01
PHYAD
AAAAA
AAAAA
REGADD
RRRRR
RRRRR
TA
Z0
10
DATA
D...........D
D...........D
IDLE
Z
Z
READ
WRITE
PRE
1.1
1.1
ST
01
01
OP
10
01
PHYAD
00000
00000
REGADD
RRRRR
RRRRR
TA
Z0
10
DATA
IDLE
Z
Z
READ
WRITE
XXXXXXXXXPPAAAAA
XXXXXXXXXPPAAAAA
Idle
Start
Opcode
(Read)
PHY Address
16h, Port 2
Register Address
MII Status, 1h
TA
Register Data
Idle
z
z
z
MDC
MDIO
(PHY)
MDIO
(STA)
z
z
0
1
1
0
1
0
1
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
z
z
Read Operation
Idle
Start
Opcode
(Write)
PHY Address
16h, Port 2
Register Address
MII Control, 0h
TA
Register Data
Idle
z
z
MDC
MDIO
(STA)
z
0
1
0
1
1
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
z
Write Operation
22235I-9
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C874VD | 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP |
| AM79C874VF | 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP |
| AM79C874VI | 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP |
| AM79C874WW | 制造商:Advanced Micro Devices 功能描述:8" WAFER, DIE IN WAFER FORM, SINGLE PORT ETHERNET 10/100 - Trays |
| AM79C875 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:NetPHY⑩ 4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver |
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