參數(shù)資料
型號(hào)： AM50DL128CG
英文描述： 2 x 64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 64 Mbit (2 M x 16-Bit) Pseudo Static RAM (Preliminary)
中文描述： 2 × 64兆位（8米× 8位/ 4米× 16位）的CMOS和64兆位（2米× 16位），偽靜態(tài)存儲(chǔ)器（初步）
文件頁(yè)數(shù)： 66/70頁(yè)
文件大?。?/td> 1042K
代理商： AM50DL128CG
May 19, 2003
Am50DL9608G
65
P R E L I M I N A R Y
FLASH ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V V
CC
, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90
°
C, V
CC
= 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
22 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Note:
Includes all pins except V
CC
. Test conditions: V
CC
= 3.0 V, one pin at a time.
BGA PACKAGE CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
FLASH DATA RETENTION
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.4
5
sec
Excludes 00h
programming
prior to erasure (Note 4)
Chip Erase Time
Am29DL640G
56
sec
Am29DL320G
28
Accelerated Word Program Time
4
120
μs
Excludes system level
overhead (Note 5)
Word Program Time
7
210
μs
Chip Program Time
(Note 3)
Am29DL640G
28
84
sec
Am29DL320G
14
42
Description
Min
Max
Input voltage with respect to V
SS
on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to V
SS
on all I/O pins
–1.0 V
V
CC
+ 1.0 V
V
CC
Current
–100 mA
+100 mA
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
11
14
pF
C
OUT
Output Capacitance
V
OUT
= 0
12
16
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
14
16
pF
C
IN3
WP#/ACC Pin Capacitance
V
IN
= 0
17
20
pF
Parameter Description
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
°
C
10
Years
125
°
C
20
Years
相關(guān)PDF資料
PDF描述
AM50DL128CH Am50DL128CH - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM52-0001 1.2 W High Efficiency Power Amplifier 800 - 960 MHz
AM52-0001SMB 1.2 W High Efficiency Power Amplifier 800 - 960 MHz
AM52-0001TR 1.2 W High Efficiency Power Amplifier 800 - 960 MHz
AM52-0002 Industrial Control IC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM50DL128CG70IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128CG70IT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128CG85IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128CG85IT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128CH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am50DL128CH - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*