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參數(shù)資料
| 型號： | AM50DL128CG85IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲器 |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | 11.60 X 8 MM, FBGA-88 |
| 文件頁數(shù)： | 55/63頁 |
| 文件大小： | 464K |
| 代理商： | AM50DL128CG85IT |
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54
Am50DL128CG
November 7, 2002
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
3. If CE#1s, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.
4. If CE#1s, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.
Figure 29.
Pseudo SRAM Write Cycle—WE# Control
Parameter
Symbol
Description
Speed
Unit
70
85
t
WC
t
WP
t
CW
t
BW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
t
CH
Write Cycle Time
Min
70
85
ns
Write Pulse Time
Min
50
60
ns
Chip Enable to End of Write
Min
60
70
ns
Data Byte Control to End of Write
Min
60
70
ns
Address Setup Time
Min
0
ns
Write Recovery Time
Min
0
ns
WE# Low to Write to Output High-Z
Max
20
ns
WE# High to Write to Output Active
Min
0
ns
Data Set-up Time
Min
30
Data Hold from Write Time
Min
0
ns
CE2 Hold Time
Min
300
μs
t
WC
t
WP
t
WR
t
CW
t
BW
Valid Data In
t
AS
t
CH
t
OEW
Addresses
A20 to A0
WE#
CE#1
CE2
LB#, UB#
D
IN
DQ15 to DQ0
D
OUT
DQ15 to DQO
t
ODW
t
DS
t
DH
High-Z
(Note 1)
(Note 3)
(Note 4)
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