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| 型號(hào)： | AM50DL128CG85IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | 11.60 X 8 MM, FBGA-88 |
| 文件頁(yè)數(shù)： | 53/63頁(yè) |
| 文件大小： | 464K |
| 代理商： | AM50DL128CG85IT |
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52
Am50DL128CG
November 7, 2002
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
Read Cycle
Notes:
1. t
OD,
t
ODo
, t
BD
, and t
ODW
are defined as the time at which
the outputs achieve the open circuit condition and are
not referenced to output voltage levels.
2. If CE#, LB#, or UB# goes low at the same time or before
WE# goes high, the outputs will remain at high impedance.
3. If CE#, LB#, or UB# goes low at the same time or after WE#
goes low, the outputs will remain at high impedance.
Figure 27.
Pseudo SRAM Read Cycle
Parameter
Symbol
Description
Speed
Unit
70
85
t
RC
t
ACC
t
CO
t
OE
t
BA
t
COE
t
OEE
t
BE
t
OD
t
ODO
t
BD
t
OH
t
PM
t
PC
t
AA
t
AOH
Read Cycle Time
Min
70
85
ns
Address Access Time
Max
70
85
ns
Chip Enable Access Time
Max
70
85
ns
Output Enable Access Time
Max
25
ns
Data Byte Control Access Time
Max
25
ns
Chip Enable Low to Output Active
Min
10
ns
Output Enable Low to Output Active
Min
0
ns
Data Byte Control Low to Output Active
Min
0
ns
Chip Enable High to Output High-Z
Max
20
ns
Output Enable High to Output High-Z
Max
20
ns
Data Byte Control High to Output High-Z
Max
20
ns
Output Data Hold from Address Change
Min
10
ns
Page Mode Time
Min
70
ns
Page Mode Cycle Time
Min
30
ns
Page Mode Address Access Time
Max
30
ns
Page Output Data Hold Time
Min
10
ns
t
RC
t
ACC
Addresses
A20 to A0
CE#1
CE2
OE#
WE#
LB#, UB#
D
OUT
DQ15 to DQ0
t
CO
t
OH
Fixed High
High-Z
High-Z
t
OE
t
BA
t
OD
t
ODO
t
BD
Valid Data Out
Indeterminate
t
BE
t
OEE
t
COE
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