參數(shù)資料
型號: AM42DL6404G85IS
廠商: SPANSION LLC
元件分類: 存儲器
英文描述: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA73
封裝: 8 X 11.60 MM, FBGA-73
文件頁數(shù): 58/61頁
文件大小: 567K
代理商: AM42DL6404G85IS
March 20, 2002
Am42DL6404G
57
P R E L I M I N A R Y
FLASH ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V V
CC
, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90
°
C, V
CC
= 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
12 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Note:
Includes all pins except V
CC
. Test conditions: V
CC
= 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25
°
C, f = 1.0 MHz.
FLASH DATA RETENTION
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.4
5
sec
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
56
sec
Byte Program Time
5
150
μs
Excludes system level
overhead (Note 5)
Accelerated Byte/Word Program Time
4
120
μs
Word Program Time
7
210
μs
Chip Program Time
(Note 3)
Byte Mode
42
126
sec
Word Mode
28
84
Description
Min
Max
Input voltage with respect to V
SS
on all pins except I/O pins
(including A9, OE#, and RESET#)
1.0 V
12.5 V
Input voltage with respect to V
SS
on all I/O pins
1.0 V
V
CC
+ 1.0 V
V
CC
Current
100 mA
+100 mA
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
11
14
pF
C
OUT
Output Capacitance
V
OUT
= 0
12
16
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
14
16
pF
C
IN3
WP#/ACC Pin Capacitance
V
IN
= 0
17
20
pF
Parameter Description
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
°
C
10
Years
125
°
C
20
Years
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AM42DL6404G85IT Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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