參數(shù)資料
型號(hào)： AM42DL6404G85IS
廠商： SPANSION LLC
元件分類： 存儲(chǔ)器
英文描述： Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 8 X 11.60 MM, FBGA-73
文件頁(yè)數(shù)： 32/61頁(yè)
文件大?。?/td> 567K
代理商： AM42DL6404G85IS
March 20, 2002
Am42DL6404G
31
P R E L I M I N A R Y
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V
CC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or one of the banks is in the erase-sus-
pend-read mode.
Table 13 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE#f to control the read cycles. When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 μs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are pro-
tected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data# Poll-
ing).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 μs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 13 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 23 in
the
“
Flash AC Characteristics
”
section shows the tog-
gle bit timing diagrams. Figure 24 shows the differ-
ences between DQ2 and DQ6 in graphical form. See
also the subsection on DQ2: Toggle Bit II.
Figure 6.
Toggle Bit Algorithm
START
No
Yes
Yes
DQ5 = 1
No
Yes
Toggle Bit
= Toggle
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Toggle Bit
= Toggle
Read Byte Twice
(DQ7
–
DQ0)
Address = VA
Read Byte
(DQ7
–
DQ0)
Address =VA
Read Byte
(DQ7
–
DQ0)
Address =VA
Note:
The system should recheck the toggle bit even if DQ5
=
“
1
”
because the toggle bit may stop toggling as DQ5
changes to
“
1.
”
See the subsections on DQ6 and DQ2 for
more information.
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