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| 型號： | AM42DL6402G |
| 英文描述： | 150NS, SOIC, IND TEMP(EEPROM) |
| 中文描述： | 64兆位（8米x8Bit/4M x16Bit）閃存和SRAM（初步） |
| 文件頁數(shù)： | 55/60頁 |
| 文件大?。?/td> | 956K |
| 代理商： | AM42DL6402G |
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54
Am42DL16x2D
March 4, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
Notes:
1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing.
1. t
CW
is measured from CE1#s going low to the end of write.
2. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CE1#s or WE# going high.
3. t
AS
is measured from the address valid to the beginning of write.
4. A write occurs during the overlap (t
WP
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP
is measured from the beginning of write
to the end of write.
Figure 31.
SRAM Write Cycle—CE1#s Control
Address
Data Valid
UB#s, LB#s
WE#
Data In
Data Out
High-Z
High-Z
t
WC
CE1#s
CE2s
t
AW
t
AS
(See Note 2 )
t
BW
t
(See Note 3)
t
WR
(See Note 4)
t
WP
(See Note 5)
t
DW
t
DH
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| AM42DL6402G70IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM |
| AM42DL6402G70IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM |
| AM42DL6402G85IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM |
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| AM42DL6404G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 4 Mbit (256 K x 16-Bit) Static RAM (Preliminary) |
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