參數(shù)資料
型號(hào): AM42DL6402G
英文描述: 150NS, SOIC, IND TEMP(EEPROM)
中文描述: 64兆位(8米x8Bit/4M x16Bit)閃存和SRAM(初步)
文件頁數(shù): 52/60頁
文件大?。?/td> 956K
代理商: AM42DL6402G
March 4, 2002
Am42DL16x2D
51
P R E L I M I N A R Y
AC CHARACTERISTICS
SRAM Read Cycle
Note:
CE1#s = OE# = V
IL
, CE2s = WE# = V
IH
, UB#s and/or LB#s = V
IL
Figure 28.
SRAM Read Cycle—Address Controlled
Parameter
Symbol
Description
Speed Options
Unit
70
85
t
RC
Read Cycle Time
Min
70
85
ns
t
AA
Address Access Time
Max
70
85
ns
t
CO1
, t
CO2
Chip Enable to Output
Max
70
85
ns
t
OE
Output Enable Access Time
Max
35
45
ns
t
BA
LB#s, UB#s to Valid Output
Max
70
85
ns
t
LZ1
, t
LZ2
Chip Enable (CE1#s Low and CE2s High) to Low-Z
Output
Min
10
ns
t
BLZ
UB#, LB# Enable to Low-Z Output
Min
10
ns
t
OLZ
Output Enable to Low-Z Output
Min
5
ns
t
HZ1
, t
HZ2
Chip disable to High-Z Output
Min
0
ns
Max
25
t
BHZ
UB#s, LB#s Disable to High-Z Output
Min
0
ns
Max
25
t
OHZ
Output Disable to High-Z Output
Min
0
ns
Max
25
t
OH
Output Data Hold from Address Change
Min
10
15
ns
Address
Data Out
Previous Data Valid
Data Valid
t
AA
t
RC
t
OH
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