- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376486 > AM41DL3208GB30IT (Spansion Inc.) LJT 79C 79#22D PIN RECP PDF資料下載
參數(shù)資料
| 型號： | AM41DL3208GB30IT |
| 廠商： | Spansion Inc. |
| 英文描述： | LJT 79C 79#22D PIN RECP |
| 中文描述： | 堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 59/65頁 |
| 文件大?。?/td> | 1288K |
| 代理商： | AM41DL3208GB30IT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當前第59頁第60頁第61頁第62頁第63頁第64頁第65頁
58
Am41DL3208G
February 13, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
SRAM Write Cycle
Notes:
1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. t
CW
is measured from CE1#s going low to the end of write.
3. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CE1#s or WE# going high.
4. t
AS
is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP
is measured from the beginning of write
to the end of write.
Figure 30.
SRAM Write Cycle
—
WE# Control
Parameter
Symbol
Description
Speed Options
Unit
70
85
t
WC
Write Cycle Time
Min
70
85
ns
t
Cw
Chip Enable to End of Write
Min
60
70
ns
t
AS
Address Setup Time
Min
0
ns
t
AW
Address Valid to End of Write
Min
60
70
ns
t
BW
UB#s, LB#s to End of Write
Min
60
70
ns
t
WP
Write Pulse Time
Min
50
60
ns
t
WR
Write Recovery Time
Min
0
ns
t
WHZ
Write to Output High-Z
Min
0
0
ns
Max
20
25
t
DW
Data to Write Time Overlap
Min
30
35
ns
t
DH
Data Hold from Write Time
Min
0
ns
t
OW
End Write to Output Low-Z
min
5
ns
Address
CS1#s
Data Undefined
UB#s, LB#s
WE#
Data In
Data Out
t
WC
t
CW
(See Note 2)
t
AW
High-Z
High-Z
Data Valid
CS2s
t
CW
(See Note 2)
t
BW
t
WP
(See Note 5)
t
AS
(See Note 4)
t
WR
(See Note 3)
t
BW
t
DW
t
DH
t
OW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM41DL3208GB35IT | Circular Connector; No. of Contacts:79; Series:MS27505; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:21; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
| AM41DL3208GB40IT | LJT 41C 41#20 PIN RECP |
| AM41DL3208GB45IT | LJT 41C 41#20 PIN WALL RECP |
| AM41DL3208GB70I | Circular Connector; No. of Contacts:41; Series:MS27505; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:21; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
| AM41DL3208GB70IT | Circular Connector; No. of Contacts:41; Series:MS27505; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:21; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM41DL3208GB35IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM |
| AM41DL3208GB40IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM |
| AM41DL3208GB45IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM41DL3208GB55IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM |
| AM41DL3208GB70I | 制造商:Spansion 功能描述:COMBO 2MX16/4MX8 FLASH + 512KX16/1MX8 SRAM 3V/3.3V 73FBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。