參數(shù)資料
型號： AM41DL3208GB30IT
廠商： Spansion Inc.
英文描述： LJT 79C 79#22D PIN RECP
中文描述： 堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁數(shù)： 4/65頁
文件大?。?/td> 1288K
代理商： AM41DL3208GB30IT
February 13, 2002
Am41DL3208G
3
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .7
Special Handling Instructions for FBGA Package ....................7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .10
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
IH
;
SRAM Word Mode, CIOs = V
CC
..................................................... 11
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
;
SRAM Byte Mode, CIOs = V
SS
......................................................12
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SS
;
SRAM Word Mode, CIOs = V
CC
.....................................................13
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
IL
; SRAM
Byte Mode, CIOs = V
..................................................................14
Word/Byte Configuration ........................................................15
Requirements for Reading Array Data ...................................15
Writing Commands/Command Sequences ............................15
Accelerated Program Operation ..........................................15
Autoselect Functions ...........................................................15
Simultaneous Read/Write Operations with Zero Latency .......15
Standby Mode ........................................................................16
Automatic Sleep Mode ...........................................................16
RESET#: Hardware Reset Pin ...............................................16
Output Disable Mode ..............................................................16
Table 5. Device Bank Division ........................................................16
Table 6. Top Boot Sector Addresses .............................................17
Top Boot SecSi
Sector Addresses............................................. 18
Table 8. Bottom Boot Sector Addresses .........................................19
Bottom Boot SecSi
Sector Addresses........................................ 20
Autoselect Mode .....................................................................21
Sector/Sector Block Protection and Unprotection ..................21
Table 10. Top Boot Sector/Sector Block Addresses
forProtection/Unprotection .............................................................21
Write Protect (WP#) ................................................................21
Temporary Sector/Sector Block Unprotect .............................22
Figure 1. Temporary Sector Unprotect Operation........................... 22
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algo-
rithms.............................................................................................. 23
SecSi (Secured Silicon) Sector Flash Memory Region ..........24
Factory Locked: SecSi Sector Programmed and Protected At
the Factory ..........................................................................24
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ...........................................................24
Hardware Data Protection ......................................................24
Low V
CC
Write Inhibit ...........................................................24
Write Pulse
“
Glitch
”
Protection ............................................24
Logical Inhibit ......................................................................24
Power-Up Write Inhibit .........................................................25
Common Flash Memory Interface (CFI) . . . . . . .25
Table 11. CFI Query Identification String........................................ 25
System Interface String................................................................... 26
Table 13. Device Geometry Definition............................................ 26
Table 14. Primary Vendor-Specific Extended Query...................... 27
Command Definitions . . . . . . . . . . . . . . . . . . . . . .28
Reading Array Data ................................................................28
Reset Command .....................................................................28
Autoselect Command Sequence ............................................28
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..29
Byte/Word Program Command Sequence .............................29
Unlock Bypass Command Sequence ..................................29
Figure 3. Program Operation......................................................... 30
Chip Erase Command Sequence ...........................................30
Sector Erase Command Sequence ........................................30
Erase Suspend/Erase Resume Commands ...........................31
Figure 4. Erase Operation.............................................................. 31
Table 15. Command Definitions (Flash Word Mode)...................... 32
Table 16. Command Definitions (Flash Byte Mode)....................... 33
Write Operation Status . . . . . . . . . . . . . . . . . . . . 34
DQ7: Data# Polling .................................................................34
Figure 5. Data# Polling Algorithm.................................................. 34
RY/BY#: Ready/Busy# ............................................................35
DQ6: Toggle Bit I ....................................................................35
Figure 6. Toggle Bit Algorithm........................................................ 35
DQ2: Toggle Bit II ...................................................................36
Reading Toggle Bits DQ6/DQ2 ...............................................36
DQ5: Exceeded Timing Limits ................................................36
DQ3: Sector Erase Timer .......................................................36
Table 17. Write Operation Status ...................................................37
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 38
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 38
Industrial (I) Devices ............................................................38
V
CC
f/V
CC
s Supply Voltage ...................................................38
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
CMOS Compatible ..................................................................39
SRAM DC and Operating Characteristics . . . . . 40
Zero-Power Flash .................................................................41
Figure 9. I
Current vs. Time (Showing Active and Automatic Sleep
Currents)........................................................................................ 41
Figure 10. Typical I
vs. Frequency............................................ 41
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 11. Test Setup.................................................................... 42
Table 18. Test Specifications .........................................................42
Key To Switching Waveforms . . . . . . . . . . . . . . . 42
Figure 12. Input Waveforms and Measurement Levels................. 42
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43
SRAM CE#s Timing ................................................................43
Figure 13. Timing Diagram for Alternating Between SRAM to Flash..
43
Flash Read-Only Operations .................................................44
Figure 14. Read Operation Timings............................................... 44
Hardware Reset (RESET#) ....................................................45
Figure 15. Reset Timings............................................................... 45
Flash Word/Byte Configuration (CIOf) ....................................46
Figure 16. CIOf Timings for Read Operations................................ 46
Figure 17. CIOf Timings for Write Operations................................ 46
Flash Erase and Program Operations ....................................47
Figure 18. Program Operation Timings.......................................... 48
Figure 19. Accelerated Program Timing Diagram.......................... 48
Figure 20. Chip/Sector Erase Operation Timings.......................... 49
Figure 21. Back-to-back Read/Write Cycle Timings...................... 50
Figure 22. Data# Polling Timings (During Embedded Algorithms). 50
Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 51
Figure 24. DQ2 vs. DQ6................................................................. 51
相關PDF資料
PDF描述
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AM41DL3208GB40IT LJT 41C 41#20 PIN RECP
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相關代理商/技術參數(shù)
參數(shù)描述
AM41DL3208GB35IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
AM41DL3208GB40IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
AM41DL3208GB45IT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM41DL3208GB55IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
AM41DL3208GB70I 制造商:Spansion 功能描述:COMBO 2MX16/4MX8 FLASH + 512KX16/1MX8 SRAM 3V/3.3V 73FBGA - Trays
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