Fusion Family of Mixed Signal FPGAs
Revision 4
2-185
Timing Characteristics
Table 2-112 2.5 V LVCMOS Low Slew
Worst-Case VCCI = 2.3 V
Applicable to Pro I/Os
Drive
Strength
Speed
Grade tDOUT
tDP
tDIN
tPY
tPYS tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
0.60
12.00 0.04
1.51
1.66
0.43
12.23 11.61 2.72
2.20
14.46 13.85
ns
–1
0.51
10.21 0.04
1.29
1.41
0.36
10.40
9.88
2.31
1.87
12.30 11.78
ns
–2
0.45
8.96
0.03
1.13
1.24
0.32
9.13
8.67
2.03
1.64
10.80 10.34
ns
8 mA
Std.
0.60
8.73
0.04
1.51
1.66
0.43
8.89
8.01
3.10
2.93
11.13 10.25
ns
–1
0.51
7.43
0.04
1.29
1.41
0.36
7.57
6.82
2.64
2.49
9.47
8.72
ns
–2
0.45
6.52
0.03
1.13
1.24
0.32
6.64
5.98
2.32
2.19
8.31
7.65
ns
12 mA
Std.
0.66
6.77
0.04
1.51
1.66
0.43
6.90
6.11
3.37
3.39
9.14
8.34
ns
–1
0.56
5.76
0.04
1.29
1.41
0.36
5.87
5.20
2.86
2.89
7.77
7.10
ns
–2
0.49
5.06
0.03
1.13
1.24
0.32
5.15
4.56
2.51
2.53
6.82
6.23
ns
16 mA
Std.
0.66
6.31
0.04
1.51
1.66
0.43
6.42
5.73
3.42
3.52
8.66
7.96
ns
–1
0.56
5.37
0.04
1.29
1.41
0.36
5.46
4.87
2.91
3.00
7.37
6.77
ns
–2
0.49
4.71
0.03
1.13
1.24
0.32
4.80
4.28
2.56
2.63
6.47
5.95
ns
24 mA
Std.
0.66
5.93
0.04
1.51
1.66
0.43
6.04
5.70
3.49
4.00
8.28
7.94
ns
–1
0.56
5.05
0.04
1.29
1.41
0.36
5.14
4.85
2.97
3.40
7.04
6.75
ns
–2
0.49
4.43
0.03
1.13
1.24
0.32
4.51
4.26
2.61
2.99
6.18
5.93
ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on