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參數(shù)資料
| 型號(hào)： | AFE1230 |
| 英文描述： | G.SHDSL ANALOG FRONT-END |
| 中文描述： | 灣SHDSL的模擬前端 |
| 文件頁(yè)數(shù)： | 6/15頁(yè) |
| 文件大?。?/td> | 313K |
| 代理商： | AFE1230 |
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AFE1230
SBWS015A
6
FIGURE 4. Internal Receive Amplifier.
Receive Amplifier
The AFE1230 receive channel includes an input amplifier
with a differential summer junction on-chip for echo cancel-
lation, as shown in Figure 4. Four external resistors are
needed with 10k
as the required value for each receiver-
input pair as well as 20k
for each hybrid-input pair. The
common-mode voltage of the receive amplifier is AV
DD
/2
(typical value is 2.5V).
Serial Digital Interface Operation
The AFE1230 digital interface uses a five-line serial interface,
signal names are: Master Clock (MCLK), Transmit Baud
Clock (txBaud), Transmit Data (txData), Receive Baud Clock
(rxBaud), and Receive Data (rxData). MCLK, txBaud, rxBaud,
and txData must come from the external DSP where data is
transmitted in synchronization with MCLK. MCLK is used as
the internal master clock to the AFE1230 and can run up to
40.8MHz. txBaud and rxBaud must be the same frequency
and synchronous with MCLK, however, the phase of these
signals may be different. Each baud period contains 48
MCLK cycles. During each baud cycle, txData will contain
two 16-bit transmit words with two control bytes. Each bit is
latched internally to the AFE at the rising edge of MCLK.
Figures 5, 6, and 7 illustrate the bit designations as well as the
proper timings required to operate the AFE1230.
MCLK:
The master clock of AFE1230 for both transmit
and receive sections, generated by the DSP. It runs at 48x the
symbol rate and can be varied from 1.28MHz to 40.8MHz
(37.12MHz for E1). MCLK must use a 50/50 duty cycle.
txBaud:
The transmit data baud clock, generated by the
DSP. txBaud is 517.33kHz for T1 and 773.33kHz for E1
(2.3Mbps). It may vary from 26.7kHz to 850kHz. A txBaud
period consists of 48 periods of the MCLK. The time (t
W
) of
the txBaud should not be smaller than one MCLK period.
Within the period of 48 MCLK clocks, the rising edge of the
txBaud can occur any time except in the period of t
F
, and the
falling edge of txBaud can occur at any time of the t
F
period.
txData:
The input digital data of AFE1230. This signal comes
from an external DSP with 48 bits per baud period. The 48 bits
include two 16-bit words of D/A converter input data and two
8-bit control bytes (see Tables IV and V). The D/A converter
is updated two times per symbol period and data is latched by
the AFE1230 on the rising edge of MCLK. txData must be
stable at least 2.5ns before the rising edge of MCLK and it must
remain stable at least 2.5ns after the rising edge of MCLK.
rxBaud:
The receive data baud clock, generated by the DSP.
rxBaud is 517.33kHz for T1 and 773.33kHz for E1 (2.3Mbps).
It may vary from 26.7kHz to 850kHz. One rxBaud period
consists of 48 periods of the MCLK. Within the period of 48
MCLK clocks, the rising edge of the rxBaud can occur at any
time except in t
F
period, and the falling edge of rxBaud can
occur at any time during t
F
. The width of the rxBaud pulse
should be no shorter than one period of MCLK.
rxData:
The output digital data of AFE1230, sent to the
external DSP with 48 bits per baud period. The 48 bits include
two 16-bit words of receive data and two 8-bit control words
(Reserved) (see Tables VI and VII). The A/D converter is
updated two times per symbol period and rxData is changed
by AFE1230 at the falling edge of MCLK. rxData is stable at
least 2.5ns before the rising edge of MCLK and it remains
stable at least 2.5ns after the rising edge of MCLK.
Internal
Amp
Vp-p
≤
6.2V
Σ
A/D Converter
R
F
R
F
hy+
rx+
hy
–
rx
–
R
3
R
4
R
5
R
6
V
rx
V
hy
External Circuit
R
3
= R
5
= 20k
R
4
= R
6
= 10k
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AFE1230E | G.SHDSL ANALOG FRONT-END |
| AFE1231K | G.SHDSL ANALOG FRONT-END |
| AFE1231KG4 | G.SHDSL ANALOG FRONT-END |
| AFE2124 | Dual HDSL/SDSL ANALOG FRONT END |
| AFE2124E | Dual HDSL/SDSL ANALOG FRONT END |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFE1230E | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1230E/1K | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1230E/1KG4 | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1230E-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1230E-1/1K | 制造商:Texas Instruments 功能描述: |
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