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參數資料
| 型號： | AFE1230 |
| 英文描述： | G.SHDSL ANALOG FRONT-END |
| 中文描述： | 灣SHDSL的模擬前端 |
| 文件頁數： | 10/15頁 |
| 文件大?。?/td> | 313K |
| 代理商： | AFE1230 |
AFE1230
SBWS015A
10
TABLE XI. Typical Performance for HDSL2 Circuit, (See
Figure 10).
PARAMETER
VALUE
Line Power
PAR
16.8
±
0.5dBm
4 (Vp/Vrms)
135
1:2.3
OPA2677
+12V
1(v/v)
2.8 (v/v)
6.2Vp-p (Differential)
17.3V (Differential)
560mW
600kHz
600kHz
Line Termination Resistance
Transformer Turns Ratio
External Driver
OPA2677 Power Supply
DC Gain
AC Gain (R Can Be Adjusted)
AFE1230 Peak-to-Peak Output Voltage
OPA2677 Peak-to-Peak Output Voltage
AFE1230 Power Dissipation
Transmit Low-Pass Filter Cutoff Frequency
Receive Low-Pass Filter (Optional) Cutoff Frequency
APPLICATIONS
AFE1230 BASIC APPLICATION CIRCUITS
There are two basic circuits for AFE1230 evaluation and
applications in this section. Figure 8 is a basic setting of a
135
line interface circuit, used to test the basic transmit and
receive functions as well as uncancelled echo of the AFE1230.
In the circuit, R
1
and R
2
are used to control far-end reflection
and maximize the energy exchange between the transmitter
and loop. The value of R
1
and R
2
, (see Figure 8), is designed
to match a 135
line with turns ratio of 1:3.7 (device:line)
transformer from Midcom (51185 Rev6A). R
4
and R
6
are line
input resistors; 10k
is a suggested value. R
3
and R
5
are
hybrid input resistors that control the echo cancellation. The
two 53nF capacitors are used for external transmit low-pass
filters with a cutoff frequency about 600kHz.
When Figure 8 is used for uncancelled echo test, it provides
total noise measurement of AFE1230 transmit and receive
paths (this includes linearity error, distortion, and noise). The
measurement of uncancelled echo is made as follows: the
AFE1230 is connected to the external circuit (see Figure 8)
and the hybrid resistors can be different values. The line is
simulated by a 135
resistor. A symbol sequence is generated
by the tester and sent to both the AFE1230 and an external
adaptive filter. The symbol sequence through the transmit
path is then loopbacked to the hybrid input and line input.
Different loopback conditions are applied in the test, such as
line input disconnected, hybrid input disconnected, or 135
resistor shorted. The output of the adaptive filter is subtracted
from the AFE1230 output to form the uncancelled echo
signal. Since there is no far-end signal source, or additive line
noise, the uncancelled echo contains only noise and linearity
errors generated in transmit and receive channels of the
AFE1230. The uncancelled echo is defined as a ratio of the
rms uncancelled echo to the rms voltage of the nominal
transmitted signal (for example 14.5dBm).
Figure 8 also shows a basic setting for G.SHDSL applica-
tions that can provide 14.5dBm power directly to a 135
line. The typical performance is listed in Table X. A power
spectrum density of a random sequence through this circuit
with 30M bit rate is shown in Figure 9.
Figure 10 is a basic application circuit with an external driver
(OPA2677) to provide 17.3dBm power on a 135
loop for
HDSL2 transmission. The analog signal from the AFE1230
has 6.2V peak-to-peak voltage and is loaded by a 1k
resistor.
The OPA2677 is configured as a wideband power amplifier
with a constant AC gain of 2.8V and 17.3V peak-to-peak
output voltage. The output signal from the OPA2677 is filtered
to minimize noise by a tx RC low-pass filter with a cutoff
frequency of 600kHz. A 1:2.3 transformer from Midcom
(51440R Rev00) is used. The receive amplifier receives far-
end signals from the line through the line transformer with 2.3
times of step down. The line input resistors of the AFE1230
are set to 10k
. The basic resistor network hybrid circuit is
used to isolate transmit signals from receivers. The receive
low-pass filter (optional) performs bandlimit to the receive
signal to minimize aliasing. Table XI gives the line interface
basic performance for HDSL2.
In practice, the line impedance is changed with frequency
under the different loop conditions. An RC or RLC compro-
mise network is generally inserted in the external hybrid path
to track the impedance over the frequency band interested. The
components of the compromise networks are adjustable for
minimizing far-end, near-end, and trans-hybrid reflections.
The coupling capacitance (0.1
μ
F) on the tx and rx paths is
used for AFE evaluation only. With the DSL external hybrid
circuit, this capacitance should be adjusted.
AFE1230 Power Dissipation
When using the on-chip driver at E1 rates, 3.3V digital power
supply (5V analog power supply) for G.SHDSL operation,
with 14.5dBm power to the line, the AFE1230 power dissipa-
tion including both analog and digital circuitry is about
750mW. Most power dissipation on the chip is in the on-chip
driver and other analog circuitry (about 120mW power dissi-
pation is from digital circuitry). Digital power dissipation is
reduced when the operating frequency decreases, but the
analog power dissipation stays the same with the frequency
changing. When an external driver (OPA2677) is used, the
power dissipation of the AFE1230 is about 560mW.
TABLE X. Typical Performance for G.SHDSL Circuit, Shown
in Figure 8.
PARAMETER
VALUE
Line Power
14.5dBm
11.7V
3.0 (Vp/Vrms)
135
1:3.7
6.2Vp-p (Differential)
600kHz
600kHz
Line Peak-to-Peak Voltage
PAR
Line Termination Resistance
Transformer Turns Ratio
AFE1230 Output Peak-to-Peak Voltage
External tx Low-Pass Filter Cutoff Frequency
External rx Low-Pass Filter (Optional) Cutoff Frequency
相關PDF資料 |
PDF描述 |
|---|---|
| AFE1230E | G.SHDSL ANALOG FRONT-END |
| AFE1231K | G.SHDSL ANALOG FRONT-END |
| AFE1231KG4 | G.SHDSL ANALOG FRONT-END |
| AFE2124 | Dual HDSL/SDSL ANALOG FRONT END |
| AFE2124E | Dual HDSL/SDSL ANALOG FRONT END |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AFE1230E | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1230E/1K | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1230E/1KG4 | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1230E-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1230E-1/1K | 制造商:Texas Instruments 功能描述: |
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