參數(shù)資料
型號(hào)： ADV7393BCPZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 5/108頁
文件大?。?/td> 0K
描述： IC DAC ENCODER VID HDTV 40-LFCSP
產(chǎn)品變化通告： ADV734x, ADV739x Feature Improvement
設(shè)計(jì)資源： Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
標(biāo)準(zhǔn)包裝： 2,500
類型： 視頻編碼器
應(yīng)用： 機(jī)頂盒，視頻播放器，顯示器
電壓 - 電源，模擬： 2.6 V ~ 3.46 V
電壓 - 電源，數(shù)字： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 帶卷 (TR)
配用： ADV7393-DBRDZ-ND - BOARD EVAL FOR ADV7393
EVAL-ADV7393EBZ-ND - BOARD EVAL FOR ADV7393 ENCODER
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 102 of 108
Table 116. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x30
0x2C
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 117. 16-Bit 720p YCrCb In, YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x30
0x28
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 118. 16-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x2C
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 119. 16-Bit 720p YCrCb In, RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x28
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 120. 16-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x30
0x6C
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 121. 16-Bit 1080i YCrCb In, YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x30
0x18
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 122. 16-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x6C
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 123. 16-Bit 1080i YCrCb In, RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x18
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 124. 8-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x2C
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 125. 10-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x2C
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x33
0x6C
10-bit input enabled.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7393-DBRDZ 功能描述:BOARD EVAL FOR ADV7393 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
ADV7393EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7393WBCPZ 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Trays
ADV7393WBCPZ-REEL 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Tape and Reel
ADV73946603 制造商:LG Corporation 功能描述:Frame Assembly
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