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參數(shù)資料
| 型號： | ADV7314KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | LEAD FREE, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 36/84頁 |
| 文件大?。?/td> | 1069K |
| 代理商： | ADV7314KST |
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REV. 0
–36–
ADV7314
Table V. Async Timing Mode Truth Table
Reference in
Figures 28a and 28b
a
b
c
d
e
P_HSYNC
1 -> 0
0
0 -> 1
1
1
P_VSYNC
0
0 -> 1
0 or 1
0 or 1
0 or 1
P_BLANK
*
0 or 1
0 or 1
0
0 -> 1
1 -> 0
50% point of falling edge of tri-level horizontal sync signal
25% point of rising edge of tri-level horizontal sync signal
50% point of falling edge of tri-level horizontal sync signal
50% start of active video
50% end of active video
*
When async timing mode is enabled,
P_BLANK
[Pin 25] becomes an active high input.
P_BLANK
is set to active low at Address 10h, Bit 6.
For standards that do not require a tri-sync level,
P_BLANK
must be tied low at all times.
HD Timing Reset
[Subaddress 14h, Bit 0]
A timing reset is achieved in setting the HD timing reset control
bit at Address 14h from 0 to 1. In this state, the horizontal and
vertical counters will remain reset. On setting this bit back to 0,
the internal counters will commence counting again.
The minimum time the pin has to be held high is one clock
cycle, otherwise this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.
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