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參數(shù)資料
| 型號： | ADV7314KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | LEAD FREE, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 19/84頁 |
| 文件大?。?/td> | 1069K |
| 代理商： | ADV7314KST |
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REV. 0
ADV7314
–19–
SR7-
SR0
00h
Register
Power
Mode
Register
Bit Description
Sleep Mode. With this control enabled, the current
consumption is reduced to A level. All DACs and
the internal PLL cct are disabled. I
2
C registers can
be read from and written to in sleep mode.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Register Setting
Sleep Mode off
Register Reset
Value (Shaded)
FCh
1
Sleep Mode on
PLL on
0
1
PLL off
DAC F off
DAC F on
DAC E off
DAC E on
DAC D off
DAC D on
DAC D off
DAC C on
DAC B off
DAC B on
DAC A off
DAC A on
Disabled
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Enabled
Cb clocked on rising edge
0
1
Y clocked on rising edge
Reserved
Clock Align
0
38h
0
1
Must be set if the phase
delay between the two
input clocks is <9.25 ns or
>27.75 ns.
SD input only
PS input only
HDTV input only
SD and PS [20-bit]
SD and PS [10-bit]
SD and HDTV [SD
oversampled
SD and HDTV [HDTV
oversampled]
PS only [at 54 MHz]
10-bit data on S Bus
10-bit data on Y Bus
Only if two input
clocks are used
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
0
1
1
1
0
1
SD Only. 10-Bit/
20-Bit Input mode
PLL and Oversampling Control. This control
allows the internal PLL cct to be powered down
and the oversampling to be switched off.
Clock Edge
Y/S Bus Swap
DAC B. Power on/off.
DAC A. Power on/off.
BTA T-1004 or 1362 Compatibility
Input Mode
Mode Select
Register
01h
DAC E. Power on/off.
Only for PS
interleaved input at
27 MHz
DAC D. Power on/off.
DAC F. Power on/off.
DAC C. Power on/off.
Only for PS dual
edge clk mode
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