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參數(shù)資料
| 型號(hào)： | ADV7314KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | LEAD FREE, MS-026BCD, LQFP-64 |
| 文件頁(yè)數(shù)： | 31/84頁(yè) |
| 文件大?。?/td> | 1069K |
| 代理商： | ADV7314KST |
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REV. 0
ADV7314
–31–
INPUT CONFIGURATION
When 10-bit input data is applied, the following bits must be
set to 1:
Address 0x7C, Bit 1 (Global 10-Bit Enable)
Address 0x13, Bit 2 (HD 10-Bit Enable)
Address 0x48, Bit 4 (SD 10-Bit Enable)
Note that the ADV7314 defaults to simultaneous standard
definition and progressive scan on power-up. Address[01h]:
Input Mode = 011.
Standard Definition Only
Address [01h] Input Mode = 000
The 8-bit/10-bit multiplexed input data is input on Pins S9–S0
(or Y9–Y0, depending on Register Address 0x01, Bit7), with S0
being the LSB in 10-bit input mode. Input standards supported
are ITU-R BT.601/656.
In 16-bit input mode, the Y pixel data is input on Pins S9–S2,
and CrCb data is input on Pins C9–C2. The 27 MHz clock
input must be input on the CLKIN_A pin.
Input sync signals are optional and are input on the
S_VSYNC
,
S_ HSYNC
, and
S_BLANK
pins.
MPEG2
DECODER
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S[9:0] or Y[9:0]
*
27MHz
3
10
YCrCb
ADV7314
*
Selected by Address 0x01 Bit 7
Figure 21 . SD Only Input Mode
Progressive Scan Only or HDTV Only
Address [01h] Input Mode 001 or 010, Respectively
YCrCb Progressive Scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data
is input on Pins Y9–Y0 and the CrCb data on Pins C9–C0. In
4:4:4 input mode, Y data is input on Pins Y9–Y0, Cb data on
Pins C9–C0, and Cr data on Pins S9–S0.
If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE
296M (720p), or BTA T-1004/1362, the async timing mode must
be used.
RGB data can be input in 4:4:4 format in PS Input mode only
or in HDTV Input mode only when HD RGB input is enabled.
G data is input on Pins Y9–Y0, R data on S9–S0, and B data
on C9–C0.
The clock signal must be input on the CLKIN_A pin.
MPEG2
DECODER
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_A
C[9:0]
10
Cb
S[9:0]
Y[9:0]
INTERLACED
TO
PROGRESSIVE
YCrCb
10
Cr
10
Y
3
27MHz
ADV7314
Figure 22. Progressive Scan Input Mode
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