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參數(shù)資料
| 型號： | ADV473KP80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | Circular Connector; No. of Contacts:55; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:17-55 |
| 中文描述： | PALETTE-DAC DSPL CTLR, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 200K |
| 代理商： | ADV473KP80 |
ADV473
–9–
REV. A
15-Bit T rue-Color Bypass Mode
Fifteen bits of pixel information may be input into the ADV473
every clock cycle. T he 15 bits of pixel information (5 bits of red,
5 bits of green, and 5 bits of blue) are input via the R0–R7 and
G0–G7 inputs.
T able V. 15-Bit T rue-Color Video Input Format
Pixel
Inputs
Input
Format
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
0
R7
R6
R5
R4
R3
G7
G6
G5
G4
G3
B7
B6
B5
B4
B3
T he 5 MSBs of the red, green, and blue DACs are driven di-
rectly by the inputs. T he 3 LSBs are a logical zero. T he color
palette RAMs and pixel read mask register are bypassed.
15-Bit T rue-Color Mode
Fifteen bits of pixel information may be input into the ADV473
every clock cycle. T he 15 bits of pixel information are input to
the device via R0–R7 and G0–G7 according to T able V. T his
input data points to the top 32 locations of the color palette
RAM, i.e., locations 223 to 255. T he 15-bit pixel input data in-
dexes a 24-bit red, green and blue value which is clocked to the
three DACs.
Overlays
T he overlay inputs, OL0–OL3, have priority regardless of the
color mode as shown in T able III.
Pixel Read Mask Register
T he 8-bit pixel read mask register is implemented as three 8-bit
pixel read mask registers, one each for the R0–R7, G0–G7, and
B0–B7 inputs. When writing to the pixel read mask register, the
same data is written to all three registers. T he read mask regis-
ters are located just before the color palette RAMs. T hus, they
are used only in the 24-bit true-color and 8-bit pseudo-color
modes since these are the only modes that use the color palette
RAMs.
T he contents of the pixel read mask register, which may be
accessed by the MPU at any time, are bit-wise logically ANDed
with the 8-bit inputs prior to addressing the color palette RAMs.
Bit D0 of the pixel read mask register corresponds to pixel input
P0 (R0, G0, or B0 depending on the mode). Bit D0 also corre-
sponds to data bus Bit D0.
VIDE O MODE S
24-Bit T rue-Color Mode
T wenty-four bits of RGB color information may be input into
the ADV473 every clock cycle. T he 24 bits of pixel information
are input via the R0–R7, G0–G7, and B0–B7 inputs. R0–R7 ad-
dress the red color palette RAM, G0–G7 address the green
color palette RAM, and B0–B7 address the blue color palette
RAM. Each RAM provides 8 bits of color information to the
corresponding D/A converter. T he pixel read mask register is
used in this mode.
24-Bit T rue-Color Bypass Mode
T wenty-four bits of pixel information may be input into the
ADV473 every clock cycle. T he 24 bits of pixel information are
input via the R0–R7, G0–G7, and B0–B7 inputs. R0–R7 drive
the red DAC directly, G0–G7 drive the green DAC directly,
and B0–B7 drive the blue DAC directly. T he color palette
RAMs and pixel read mask register are bypassed.
8-Bit Pseudo-Color Mode
Eight bits of pixel information may be input into the ADV473
every clock cycle. T he 8 bits of pixel information (P0–P7) are
input via the R0–R7, G0–G7 or B0–B7 inputs, as specified by
CR7 and CR6. All three color palette RAMs are addressed by
the same 8 bits of pixel data (P0–P7). Each RAM provides 8
bits of color information to the corresponding D/A converter.
T he pixel read mask register is used in this mode.
8-Bit T rue-Color Bypass Mode
Eight bits of pixel information may be input into the ADV473
every clock cycle. T he 8 bits of pixel information are input via
the R0–R7, G0–G7 or B0–B7 inputs, as specified by CR7 and
CR6.
T able IV. 8-Bit T rue-Color Bypass Video Input Format
R0–R7
Inputs
Selected
G0–G7
Inputs
Selected
B0–B7
Input
Selected
Inputs
Format
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
R7
R6
R5
G7
G6
G5
B7
B6
As seen in the table, 3 bits of red, 3 bits of green, and 2 bits of
blue data are input. T he 3 MSBs of the red and green DACs are
driven directly by the inputs, while the 2 MSBs of the blue DAC
are driven directly. T he 5 LSBs for the red and green DACs,
and the 6 LSBs for the blue DAC, are a logical zero. T he color
palette RAMs and pixel read mask register are bypassed.
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相關(guān)代理商/技術(shù)參數(shù) |
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