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參數(shù)資料
| 型號(hào)： | ADV473KP80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | Circular Connector; No. of Contacts:55; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:17-55 |
| 中文描述： | PALETTE-DAC DSPL CTLR, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 200K |
| 代理商： | ADV473KP80 |
ADV473
–3–
REV. A
TIMNGCHARACTERISTICS
1
(V
AA2
= 5 V; V
REF
= 1.235 V; R
L
= 37.5
, C
L
= 10 pF; R
SET
= 140
.
135 MHz
110 MHz
Parameter
Version
Version
All specifications T
MN
to T
MAX3
unless otherwse noted.)
80 MHz
Version
66 MHz
Version
Units
Conditions/Comments
fmax
t
1
t
2
t
34
t
44
t
55
t
65
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
t
18
t
SK
t
PD
135
10
10
3
40
20
5
10
10
100
50
40
2
2
7.4
3
2
30
3
13
2
4
×
t
14
110
10
10
3
40
20
5
10
10
100
50
40
3
3
9.1
3.5
3
30
3
13
2
4
×
t
14
80
10
10
3
40
20
5
10
10
100
50
40
3
3
12.5
4
4
30
3
13
2
4
×
t
14
66
10
10
3
40
20
5
10
10
100
50
40
3
3
15.15
5
5
30
3
13
2
4
×
t
14
MHz
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns typ
ns max
ns max
ns
Clock Rate
RS0–RS2 Setup T ime
RS0–RS2 Hold T ime
RD
Asserted to Data Bus Driven
RD
Asserted to Data Valid
RD
Negated to Data Bus 3-Stated
Read Data Hold T ime
Write Data Setup T ime
Write Data Hold T ime
CR0–CR3 Delay T ime
RD
,
WR
Pulse Width Low
RD
,
WR
Pulse Width High
Pixel & Control Setup T ime
Pixel & Control Hold T ime
Clock Cycle T ime
Clock Pulse Width High T ime
Clock Pulse Width Low T ime
Analog Output Delay
Analog Output Rise/Fall T ime
Analog Output Settling T ime
Analog Output Skew
Pipeline Delay
NOT ES
1
T T L input values are 0 to 3 volts, with input rise/fall times
≤
3 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs and
outputs. Analog output load
≤
10 pF, D0-D7 output load
≤
50 pF. See timing notes in Figure 2.
2
V
= 5 V
±
5%.
3
T emperature range (T
to T
); 0
°
C to +70
°
C; T
(Silicon Junction T emperature)
≤
100
°
C .
4
t
3
and t
4
are measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.4 V or 2.4 V.
5
t
and t
are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 3. T he measured number is
then extrapolated back to remove the effects of charging the 50 pF capacitor. T his means that the times, t
5
and t
6
, quoted in the timing characteristics are the
true values for the device and, as such, are independent of external bus loading capacitances.
6
Settling time does not include clock and data feedthrough.
Specifications subject to change without notice.
RS0, RS1,
RS2
D0–D7
(READ)
D0–D7
(WRITE)
RD, WR
DATA OUT (RD = 0)
DATA IN (WR = 0)
VALID
CR0–CR3
t
4
t
3
t
1
t
2
t
10
t
5
t
11
t
6
t
8
t
7
t
9
Figure 1. MPU Read/Write Timing
DATA
t
12
IOR, IOG, IOB
NOTES
1. OUTPUT DELAY MEASURED FROM THE 50% POINT OF THE RISING EDGE
OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. SETTLING TIME MEASURED FROM THE 50% POINT OF FULL-SCALE
TRANSITION TO THE OUTPUT REMAINING WITHIN
±
1 LSB.
3. OUTPUT RISE/FALL TIME MEASURED BETWEEN THE 10% AND 90%
POINTS OF FULL-SCALE TRANSITION.
CLOCK
R0-R7, G0–G7,
B0–B7,
OL0-OL3, S0–S1,
SYNC, BLANK
t
14
t
16
t
15
t
19
t
18
t
13
t
17
Figure 2. Video Input/Output Timing
3.2mA
+2.1V
TO
OUTPUT
PIN
50pF
400
μ
A
Figure 3. Load Circuit for Bus
Access and Relinquish Time
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