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參數(shù)資料
| 型號： | ADV473KP80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | Circular Connector; No. of Contacts:55; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:17-55 |
| 中文描述： | PALETTE-DAC DSPL CTLR, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 200K |
| 代理商： | ADV473KP80 |
ADV473
–11–
REV. A
PC BOARD LAY OUT CONSIDE RAT IONS
T he layout should be optimized for lowest noise on the ADV473
power and ground lines by shielding the digital inputs and pro-
viding good decoupling. T he lead length between groups of V
AA
and GND pins should be minimized so as to minimize inductive
ringing.
Ground Planes
T he ground plane should encompass all ADV473 ground pins,
current/voltage reference circuitry, power supply bypass circuitry
for the ADV473, the analog output traces, and all the digital sig-
nal traces leading up to the ADV473.
Power Planes
T he ADV473 and any associated analog circuitry should have its
own power plane, referred to as the analog power plane. T his
power plane should be connected to the regular PCB power
plane (V
CC
) at a single point through a ferrite bead, as illustrated
in Figures 7 and 8. T his bead should be located within three
inches of the ADV473.
T he PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV473 power pins and voltage reference circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane, unless they can be
arranged such that the plane-to-plane noise is common mode.
Supply Decoupling
For optimum performance, bypass capacitors should be installed
using the shortest leads possible, consistent with reliable opera-
tion, to reduce the lead inductance. Best performance is ob-
tained with a 0.1
μ
F ceramic capacitor decoupling each of the
two groups of V
AA
pins to GND. T hese capacitors should be
placed as close as possible to the device.
It is important to note that while the ADV473 contains circuitry
to reject power supply noise, this rejection decreases with fre-
quency. If a high frequency switching power supply is used, the
designer should pay close attention to reducing power supply
noise and should consider using a three-terminal voltage regula-
tor for supplying power to the analog power plane.
Digital Signal Interconnect
T he digital inputs to the ADV473 should be isolated as much as
possible from the analog outputs and other analog circuitry.
Also, these input signals should not overlay the analog power
plane.
Due to the high clock rates involved, long clock lines to the
ADV473 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (V
CC
), and not to the
analog power plane.
ANALOG POWER PLANE
IOR
IOG
IOB
V
AA
ADV473
V
REFIN
75
75
V
REFOUT
CO-AXIAL CABLE
(75
)
GND
CONBNC
75
75
75
M(CRT)
0.1
μ
F
10
μ
F
POWER SUPPLY DECOUPLING
(0.1
μ
F CAPACITOR FOR
EACH V
REF
GROUP)
0.1
μ
F
L1
(BEAD)
COMP
COMP
+5V (V
AA
)
0.1
μ
F
+5V (V
AA
)
+5V (V
CC
)
+5V (V
AA
)
0.1
μ
F
1k
AD589
(1.2 V
REF
)
COMPONENT
DESCRIPTION
0.1
μ
F CERAMIC CAPACITOR
10
μ
F TANTALUM CAPACITOR
FERRITE BEAD
75
1% METAL FILM RESISTOR
1k
5% RESISTOR
1% METAL FILM RESISTOR
1.23V VOLTAGE REFERENCE
VENDOR PART NUMBER
C1 – C5
C6
L1
R1, R2, R3
R4
R
SET
Z1
ERIE RPE112Z5U104M50V
MALLORY CSR13G106KM
FAIR-RITE 2743001111
AD589JN
R
SET
140
R
SET
0.1
μ
F
75
Figure 7. Typical Connection Diagram (External Voltage
Reference)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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