參數(shù)資料
型號(hào): ADUM1310BRWZ
廠商: ANALOG DEVICES INC
元件分類: 其它接口
英文描述: Triple-Channel Digital Isolator with Programmable Default Output
中文描述: SPECIALTY INTERFACE CIRCUIT, PDSO16
封裝: ROHS COMPLIANT, MS-013AA, SOIC-16
文件頁數(shù): 14/16頁
文件大小: 229K
代理商: ADUM1310BRWZ
ADuM1310
POWER-UP/POWER-DOWN CONSIDERATIONS
Given that the ADuM1310 has separate supplies on either side
of the isolation barrier, the power-up and power-down
characteristics relative to each supply voltage need to be
considered individually.
Rev. E | Page 14 of 16
As shown in Table 9, when V
DD1
input power is off, the
ADuM1310 outputs take on a default condition as determined
by the state of the CTRL pin. As the V
DD1
supply is
increased/decreased, the output of each channel transitions
from/to the default condition to/from the state matching its
respective signals (see Figure 13 and Figure 14).
V
DD1
OUTPUT
DATA
OUTPUT
DATA
CTRL = HIGH OR NC
Figure 13. V
DD1
Power-Up/Power-Down Characteristics, Input Data = High
CTRL = LOW
V
DD1
2V
(TYP)
0
V
DD1
OUTPUT DATA
OUTPUT
DATA
CTRL = HIGH OR NC
CTRL = LOW
V
DD1
2V
(TYP)
0
Figure 14. V
DD1
Power-Up/Power-Down Characteristics, Input Data = Low
When V
DD1
crosses the threshold for activating the refresh
circuit (approximately 2 V), there can be a delay of up to 2 μs
before the output is updated to the correct state, depending on
the timing of the next refresh pulse. When V
DD1
is reduced from
an on state below the 2 V threshold, there can be a delay of up
to 5 μs before the output takes on its default state determined by
the CTRL signal. This corresponds to the duration that the
watchdog timer circuit at the input is designed to wait before
triggering an output default state.
When the V
DD2
output supply is below the level at which the
ADuM1310 output transistors are biased (about 1 V), the
outputs take on a high impedance state. When V
DD2
is above a
value of about 2 V, each channel output takes on a state
matching that of its respective input. Between the values of 1 V
and 2 V, the outputs are set low. This behavior is shown in
Figure 15 and Figure 16.
V
DD2
OUTPUT
DATA
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 15. V
DD2
Power-Up/Power-Down Characteristics, Input Data = High
2V
(TYP)
0
V
DD2
OUTPUT
DATA
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 16. V
DD2
Power-Up/Power-Down Characteristics, Input Data = Low
2V
(TYP)
0
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