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參數(shù)資料
| 型號： | ADUM1310BRWZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | Triple-Channel Digital Isolator with Programmable Default Output |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PDSO16 |
| 封裝： | ROHS COMPLIANT, MS-013AA, SOIC-16 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 229K |
| 代理商： | ADUM1310BRWZ |
ADuM1310
APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM1310 digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 9). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for V
DD1
and between Pin 15 and Pin 16
for V
DD2
. The capacitor value should be between 0.01 μF and
0.1 μF. The total lead length between both ends of the capacitor
and the input power supply pin should not exceed 20 mm.
Bypassing between Pin 1 and Pin 8 and between Pin 9 and
Pin 16 should also be considered unless the ground pair on
each package side is connected close to the package.
Rev. E | Page 12 of 16
V
GND
1
V
IA
V
IB
V
IC
NC
DISABLE
GND
1
V
GND
2
V
OA
V
OB
V
OC
NC
CTRL
GND
2
NC = NO CONNECT
0
Figure 9. Recommended Printed Circuit Board Layout
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the length of
time it takes for a logic signal to propagate through a component.
The input to output propagation delay time for a high to low
transition may differ from the propagation delay time of a low
to high transition.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
0
Figure 10. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM1310 component.
Propagation delay skew refers to the maximum amount
the propagation delay differs among multiple ADuM1310
components operated under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent via the transformer to
the decoder. The decoder is bistable, and is, therefore, either set
or reset by the pulses indicating input logic transitions. In the
absence of logic transitions at the input for more than 2 μs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no pulses for more than about 5 μs, the input side is
assumed to be unpowered or nonfunctional, in which case, the
isolator output is forced to a default state (see Table 9) by the
watchdog timer circuit.
The magnetic field immunity of the ADuM1310 is determined by
the changing magnetic field which induces a voltage in the trans-
former’s receiving coil large enough to either falsely set or reset
the decoder. The following analysis defines the conditions
under which this can occur. The ADuM1310’s 3 V operating
condition is examined because it represents the most
susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold of about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V
= (
dβ/dt
)
∑
π
r
n2
; n
= 1, 2, … ,
N
where:
β
is the magnetic flux density (gauss).
N
is the number of turns in the receiving coil.
r
n
is the radius of the
n
th
turn in the receiving coil (cm).
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| ADUM1310BRWZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Triple-Channel Digital Isolators |
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| ADUM1310BRWZ-RL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Triple-Channel Digital Isolators |
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