1 Temperature Range –40°C to +85°C. 2
參數(shù)資料
型號(hào)： ADUC842BCPZ8-5
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 67/88頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8KB FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： DMA，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 托盤
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 7 of 88
1 Temperature Range –40°C to +85°C.
2 ADC linearity is guaranteed during normal MicroConverter core operation.
3 ADC LSB size = VREF/212, i.e., for internal VREF = 2.5 V, 1 LSB = 610 V, and for external VREF = 1 V, 1 LSB = 244 V.
4 These numbers are not production tested but are supported by design and/or characterization data on production release.
5 Offset and gain error and offset and gain error match are measured after factory calibration.
6 Based on external ADC system components, the user may need to execute a system calibration to remove additional external channel errors to achieve these
specifications.
7 SNR calculation includes distortion and noise components.
8 Channel-to-channel crosstalk is measured on adjacent channels.
9 The temperature monitor gives a measure of the die temperature directly; air temperature can be inferred from this result.
10 DAC linearity is calculated using:
Reduced code range of 100 to 4095, 0 V to VREF range.
Reduced code range of 100 to 3945, 0 V to VDD range.
DAC output load = 10 k and 100 pF.
11 DAC differential nonlinearity specified on 0 V to VREF and 0 V to VDD ranges.
12 DAC specification for output impedance in the unbuffered case depends on DAC code.
13 DAC specifications for ISINK, voltage output settling time, and digital-to-analog glitch energy depend on external buffer implementation in unbuffered mode. DAC in
unbuffered mode tested with OP270 external buffer, which has a low input leakage current.
14 Measured with CREF pin decoupled with 0.47 F capacitor to ground. Power-up time for the internal reference is determined by the value of the decoupling capacitor
chosen for the CREF pin.
15 When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit.
16 Flash/EE memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.
17 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40°C, +25°C, and +85°C. Typical endurance at 25°C is 700,000 cycles.
18 Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature as shown in Figure 38 in the Flash/EE Memory Reliability section.
19 Power supply current consumption is measured in normal, idle, and power-down modes under the following conditions:
Normal Mode:
Reset = 0.4 V, digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON (ADuC842/ADuC843), core executing internal
software loop.
Idle Mode:
Reset = 0.4 V, digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON (ADuC842/ADuC843), PCON.0 = 1, core execution
suspended in idle mode.
Power-Down Mode:
Reset = 0.4 V, all Port 0 pins = 0.4 V, All other digital I/O and Port 1 pins are open circuit, Core Clk changed via CD bits in PLLCON
(ADuC842/ADuC843), PCON.0 = 1, core execution suspended in power-down mode, OSC turned on or off via OSC_PD bit (PLLCON.7) in
PLLCON SFR (ADuC842/ADuC843).
20 DVDD power supply current increases typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
21 Power supply currents are production tested at 5.25 V and 3.3 V for a 5 V and 3 V part, respectively.
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