參數(shù)資料
型號(hào)： ADUC842BCPZ8-5
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 41/88頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8KB FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： DMA，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 托盤
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 46 of 88
SPICON SPI Control Register
SFR Address
F8H
Power-On Default
04H
Bit Addressable
Yes
Table 18. SPICON SFR Bit Designations
Bit No.
Name
Description
7
ISPI
SPI Interrupt Bit.
Set by the MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
6
WCOL
Write Collision Error Bit.
Set by the MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
5
SPE
SPI Interface Enable Bit.
Set by the user to enable the SPI interface.
Cleared by the user to enable the I2C pins, this is not requiredto enable the I2C interface if the MSPI bit is set in
CFG841/CFG842. In this case, the I2C interface is automatically enabled.
4
SPIM
SPI Master/Slave Mode Select Bit.
Set by the user to enable master mode operation (SCLOCK is an output).
Cleared by the user to enable slave mode operation (SCLOCK is an input).
3
CPOL1
Clock Polarity Select Bit.
Set by the user if SCLOCK idles high.
Cleared by the user if SCLOCK idles low.
2
CPHA1
Clock Phase Select Bit.
Set by the user if leading SCLOCK edge is to transmit data.
Cleared by the user if trailing SCLOCK edge is to transmit data.
1
SPR1
SPI Bit Rate Select Bits.
0
SPR0
These bits select the SCLOCK rate (bit rate) in master mode as follows:
SPR1
SPR0
Selected Bit Rate
0
fOSC/2
0
1
fOSC/4
1
0
fOSC/8
1
fOSC/16
In SPI slave mode, i.e., SPIM = 0, the logic level on the external SS pin can be read via the SPR0 bit.
1The CPOL and CPHA bits should both contain the same values for master and slave devices.
SPIDAT
SPI Data Register
Function
SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to
read data just received by the SPI interface.
SFR Address
F7H
Power-On Default
00H
Bit Addressable
No
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