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參數(shù)資料
| 型號(hào)： | ADUC832BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | PLASTIC, MQFP-52 |
| 文件頁(yè)數(shù)： | 64/80頁(yè) |
| 文件大?。?/td> | 1311K |
| 代理商： | ADUC832BS |
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REV. 0
–64–
ADuC832
the oscillator, can also be enabled during power down. All other
on-chip peripherals however, are shut down. Port pins retain
their logic levels in this mode, but the DAC output goes to a
high impedance state (three-state). During full power-down
mode, the ADuC832 consumes a total of approximately 20
μ
A.
There are five ways of terminating power-down mode:
Asserting the RESET pin (Pin 15)
Returns to normal mode. All registers are set to their default
state and program execution starts at the reset vector once the
Reset pin is deasserted.
Cycling Power
All registers are set to their default state and program execution
starts at the reset vector approximately 128 ms later.
Time Interval Counter (TIC) Interrupt
Power-down mode is terminated and the CPU services the TIC
interrupt. The RETI at the end of the TIC ISR will return the
core to the instruction after the one that enabled power-down.
I
2
C or SPI Interrupt
Power-down mode is terminated and the CPU services the
I
2
C/SPI interrupt. The RETI at the end of the ISR will return the
core to the instruction after the one that enabled power-down. It
should be noted that the I
2
C/SPI power-down interrupt enable
bit (SERIPD) in the PCON SFR must first be set to allow this
mode of operation.
INT0
Interrupt
Power-down mode is terminated and the CPU services the
INT0
interrupt. The RETI at the end of the ISR will return the
core to the instruction after the one that enabled power-down.
The
INT0
pin must not be driven low during or within 2 machine
cycles of the instruction that initiates power-down mode. It
should be noted that the
INT0
power-down interrupt enable bit
(INT0PD) in the PCON SFR must first be set to allow this
mode of operation.
Power-On Reset
An internal POR (Power-On Reset) is implemented on the
ADuC832. For DV
DD
below 2.45 V, the internal POR will hold
the ADuC832 in reset. As DV
DD
rises above 2.45 V, an internal
timer will timeout for 128 ms approximately before the part is
released from reset. The user must ensure that the power supply
has reached a stable 2.7 V minimum level by this time. Likewise
on power-down, the internal POR will hold the ADuC832 in
reset until the power supply has dropped below 1 V. Figure 62
illustrates the operation of the internal POR in detail.
128ms TYP
1.0V TYP
128ms TYP
2.45V TYP
1.0V TYP
INTERNAL
CORE RESET
DV
DD
Figure 62. Internal POR Operation
Grounding and Board Layout Recommendations
As with all high resolution data converters, special attention
must be paid to grounding and PC board layout of ADuC832-
based designs in order to achieve optimum performance from
the ADC and DACs.
Although the ADuC832 has separate pins for analog and digital
ground (AGND and DGND), the user must not tie these to two
separate ground planes unless the two ground planes are connected
together very close to the ADuC832, as illustrated in the simpli-
fied example of Figure 63a. In systems where digital and analog
ground planes are connected together somewhere else (at the
system
’
s power supply for example), they cannot be connected
again near the ADuC832 since a ground loop would result. In
these cases, tie the ADuC832
’
s AGND and DGND pins all to
the analog ground plane, as illustrated in Figure 63b. In systems
with only one ground plane, ensure that the digital and analog
components are physically separated onto separate halves of the
board such that digital return currents do not flow near analog
circuitry and vice versa. The ADuC832 can then be placed between
the digital and analog sections, as illustrated in Figure 63c.
In all of these scenarios, and in more complicated real-life appli-
cations, keep in mind the flow of current from the supplies and
back to ground. Make sure the return paths for all currents are as
close as possible to the paths the currents took to reach their desti-
nations. For example, do not power components on the analog
side of Figure 63b with DV
DD
since that would force return currents
from DV
DD
to flow through AGND. Also, try to avoid digital
currents flowing under analog circuitry, which could happen if
the user placed a noisy digital chip on the left half of the board
in Figure 63c. Whenever possible, avoid large discontinuities in
the ground plane(s) (such as are formed by a long trace on the
same layer), since they force return signals to travel a longer path.
And of course, make all connections to the ground plane directly,
with little or no trace separating the pin from its via to ground.
If the user plans to connect fast logic signals (rise/fall time < 5ns)
to any of the ADuC832
’
s digital inputs, add a series resistor to
each relevant line to keep rise and fall times longer than 5 ns at
the ADuC832 input pins. A value of 100
or 200
is usually
sufficient to prevent high speed signals from coupling capacitively
into the ADuC832 and affecting the accuracy of ADC conversions.
b.
DGND
AGND
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
c.
GND
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
a.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
DGND
AGND
Figure 63. System Grounding Schemes
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