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| 型號： | ADUC832BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | PLASTIC, MQFP-52 |
| 文件頁數(shù)： | 49/80頁 |
| 文件大小： | 1311K |
| 代理商： | ADUC832BS |
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REV. 0
ADuC832
–49–
In general-purpose I/O port mode, Port 2 pins that have 1s written
to them are pulled high by the internal pull-ups (Figure 39)
and, in that state, can be used as inputs. As inputs, Port 2 pins
being pulled externally low will source current because of the
internal pull-up resistors. Port 2 pins with 0s written to them will
drive a logic low output voltage (V
OL
) and will be capable of
sinking 1.6 mA.
P2.6 and P2.7 can also be used as PWM outputs. In the case
that they are selected as the PWM outputs via the CFG832 SFR,
the PWM outputs will overwrite anything written to P2.6 or P2.7.
CONTROL
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
LATCH
Q
Q
DV
DD
ADDR
P2.x
PIN
DV
DD
INTERNAL
PULL-UP
*
*
SEE FIGURE 39 FOR
DETAILS OF INTERNAL PULL-UP
Figure 38. Port 2 Bit Latch and I/O Buffer
Q
FROM
PORT
LATCH
2 CLK
DELAY
Q1
DV
DD
Q2
DV
DD
Q3
DV
DD
Px.x
PIN
Q4
Figure 39. Internal Pull-Up Configuration
Port 3
Port 3 is a bidirectional port with internal pull-ups directly
controlled via the P3 SFR. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and, in that state,
can be used as inputs. As inputs, Port 3 pins being pulled exter-
nally low will source current because of the internal pull-ups.
Port 3 pins with 0s written to them will drive a logic low output
voltage (V
OL
) and will be capable of sinking 4 mA.
Port 3 pins also have various secondary functions described in
Table XIX. The alternate functions of Port 3 pins can only be
activated if the corresponding bit latch in the P3 SFR contains a 1.
Otherwise, the port pin is stuck at 0.
Table XIX. Port 3, Alternate Pin Functions
Pin
Alternate Function
P3.0
P3.1
RxD (UART Input Pin)(or Serial Data I/O in Mode 0)
TxD (UART Output Pin)
(or Serial Clock Output in Mode 0)
INT0
(External Interrupt 0)
INT1
(External Interrupt 1)/PWM 1/MISO
T0 (Timer/Counter 0 External Input)
PWM External Clock/PWM 0
T1 (Timer/Counter 1 External Input)
WR
(External Data Memory Write Strobe)
RD
(External Data Memory Read Strobe)
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.3 and P3.4 can also be used as PWM outputs. In the case
that they are selected as the PWM outputs via the CFG832 SFR,
the PWM outputs will overwrite anything written to P3.4 or P3.3.
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
LATCH
Q
Q
DV
DD
P3.x
PIN
INTERNAL
PULL-UP
*
*
SEE FIGURE 39
FOR DETAILS OF
INTERNAL PULL-UP
ALTERNATE
OUTPUT
FUNCTION
ALTERNATE
INPUT
FUNCTION
Figure 40. Port 3 Bit Latch and I/O Buffer
Additional Digital I/O
In addition to the port pins, the dedicated SPI/I
2
C pins (SCLOCK
and SDATA/MOSI) also feature both input and output functions.
Their equivalent I/O architectures are illustrated in Figure 41
and Figure 43, respectively, for SPI operation and in Figure 42
and Figure 44 for I
2
C operation.
Notice that in I
2
C mode (SPE = 0), the strong pull-up FET
(Q1) is disabled, leaving only a weak pull-up (Q2) present.
By contrast, in SPI mode (SPE = 1) the strong pull-up FET
(Q1) is controlled directly by SPI hardware, giving the pin
push-pull capability.
In I
2
C mode (SPE = 0), two pull-down FETs (Q3 and Q4) operate
in parallel in order to provide an extra 60% or 70% of current
sinking capability. In SPI mode, however, (SPE = 1) only one of
the pull-down FETs (Q3) operates on each pin resulting in sink
capabilities identical to that of Port 0 and Port 2 pins.
On the input path of SCLOCK, notice that a Schmitt trigger
conditions the signal going to the SPI hardware to prevent false
triggers (double triggers) on slow incoming edges. For incoming
signals from the SCLOCK and SDATA pins going to I
2
C hard-
ware, a filter conditions the signals in order to reject glitches of
up to 50 ns in duration.
Notice also that direct access to the SCLOCK and SDATA/MOSI
pins is afforded through the SFR interface in I
2
C master mode.
Therefore, if you are not using the SPI or I
2
C functions, you can
use these two pins to give additional high current digital outputs.
HARDWARE SPI
(MASTER/SLAVE)
Q3
SCHMITT
TRIGGER
Q1
Q2 (OFF)
DV
DD
SCLOCK
PIN
Q4 (OFF)
SPE = 1 (SPI ENABLE)
Figure 41. SCLOCK Pin I/O Functional Equivalent
in SPI Mode
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