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參數(shù)資料
| 型號： | ADUC832BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | PLASTIC, MQFP-52 |
| 文件頁數(shù)： | 44/80頁 |
| 文件大?。?/td> | 1311K |
| 代理商： | ADUC832BS |
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REV. 0
–44–
ADuC832
POWER SUPPLY MONITOR
As its name suggests, the Power Supply Monitor, once enabled,
monitors the DV
DD
supply on the ADuC832. It will indicate when
any of the supply pins drop below one of four user-selectable
voltage trip points from 2.63 V to 4.37 V. For correct operation
of the Power Supply Monitor function, AV
DD
must be equal to
or greater than 2.7 V. Monitor function is controlled via the
PSMCON SFR. If enabled via the IEIP2 SFR, the monitor will
interrupt the core using the PSMI bit in the PSMCON SFR.
This bit will not be cleared until the failing power supply has
returned above the trip point for at least 250 ms. This monitor
function allows the user to save working registers to avoid pos-
sible data loss due to the low supply condition, and also ensures
that normal code execution will not resume until a safe supply
level has been well established. The supply monitor is also pro-
tected against spurious glitches triggering the interrupt circuit.
PSMCON
SFR Address
Power-On Default Value
Bit Addressable
Power Supply Monitor Control Register
DFH
DEH
No
Table XV. PSMCON SFR Bit Designations
Bit
Name
Description
7
6
----
CMPD
Reserved.
DV
DD
Comparator Bit.
This is a read-only bit and directly reflects the state of the DV
DD
comparator.
Read
“
1
”
indicates the DV
DD
supply is above its selected trip point.
Read
“
0
”
indicates the DV
DD
supply is below its selected trip point.
Power Supply Monitor Interrupt Bit.
This bit will be set high by the MicroConverter if either CMPA or CMPD is low, indicating low analog
or digital supply. The PSMI bit can be used to interrupt the processor. Once CMPD and/or CMPA
return (and remain) high, a 250 ms counter is started. When this counter times out, the PSMI interrupt is
cleared. PSMI can also be written by the user. However, if either comparator output is low, it is not
possible for the user to clear PSMI.
DV
DD
Trip Point Selection Bits.
These bits select the DV
DD
trip point voltage as follows:
TPD1
TPD0
Selected DV
DD
Trip Point (V)
0
0
4.37
0
1
3.08
1
0
2.93
1
1
2.63
Reserved
Reserved
Power Supply Monitor Enable Bit.
Set to
“
1
”
by the user to enable the Power Supply Monitor Circuit.
Cleared to
“
0
”
by the user to disable the Power Supply Monitor Circuit.
5
PSMI
4
3
TPD1
TPD0
2
1
0
----
----
PSMEN
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