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參數(shù)資料
| 型號(hào)： | ADUC816BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 49/68頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 52MQFP |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 7x16b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 738 (CN2011-ZH PDF) |
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REV. 0
ADuC816
–53–
TCON: Timer/Counter 0 and 1 Control Register
SFR Address
88H
Power-On Default Value
00H
Bit Addressable
Yes
1
F
T1
R
T0
F
T0
R
T1
E
I
1
T
I
1
0
E
I
1
0
T
I
1
NOTE
1These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external
INT0 and INT1 interrupt pins.
Table XXIV. TCON SFR Bit Designations
Bit
Name
Description
7
TF1
Timer 1 Overflow Flag.
Set by hardware on a timer/counter 1 overflow.
Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine.
6
TR1
Timer 1 Run Control Bit.
Set by user to turn on timer/counter 1.
Cleared by user to turn off timer/counter 1.
5
TF0
Timer 0 Overflow Flag.
Set by hardware on a timer/counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
4
TR0
Timer 0 Run Control Bit.
Set by user to turn on timer/counter 0.
Cleared by user to turn off timer/counter 0.
3
IE1
External Interrupt 1 (
INT1) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin
INT1, depend-
ing on bit IT1 state.
Cleared by hardware when the when the PC vectors to the interrupt service routine only if the inter-
rupt was transition-activated. If level-activated, the external requesting source controls the
request flag, rather than the on-chip hardware.
2
IT1
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
1
IE0
External Interrupt 0 (
INT0) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin
INT0, depend-
ing on bit IT0 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was
transition-activated. If level-activated, the external requesting source controls the request flag,
rather than the on-chip hardware.
0
IT0
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit register
depending on the timer mode configuration.
TH0 and TL0
Timer 0 high byte and low byte.
SFR Address = 8Chex, 8Ahex respectively.
TH1 and TL1
Timer 1 high byte and low byte.
SFR Address = 8Dhex, 8Bhex respectively.
REV. A
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