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ADuC816
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NONVOLATILE FLASH/EE MEMORY
Flash/EE Memory Overview
The ADuC816 incorporates Flash/EE memory technology on-chip
to provide the user with nonvolatile, in-circuit reprogrammable,
code and data memory space.
Flash/EE memory is a relatively recent type of nonvolatile memory
technology and is based on a single transistor cell architecture.
This technology is basically an outgrowth of EPROM technology
and was developed through the late 1980s. Flash/EE memory takes
the flexible in-circuit reprogrammable features of EEPROM and
combines them with the space efficient/density features of EPROM
(see Figure 25).
Because Flash/EE technology is based on a single transistor cell
architecture, a Flash memory array, like EPROM, can be imple-
mented to achieve the space efficiencies or memory densities
required by a given design.
Like EEPROM, Flash memory can be programmed in-system at
a byte level, although it must first be erased; the erase being per-
formed in page blocks. Thus, Flash memory is often and more
correctly referred to as Flash/EE memory.
FLASH/EE MEMORY
TECHNOLOGY
SPACE EFFICIENT/
DENSITY
IN-CIRCUIT
REPROGRAMMABLE
EPROM
TECHNOLOGY
EEPROM
TECHNOLOGY
Figure 25. Flash/EE Memory Development
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit program-
mability, high density and low cost. Incorporated in the ADuC816,
Flash/EE memory technology allows the user to update program
code space in-circuit, without the need to replace one-time
programmable (OTP) devices at remote operating nodes.
Flash/EE Memory and the ADuC816
The ADuC816 provides two arrays of Flash/EE memory for user
applications. 8K bytes of Flash/EE Program space are provided
on-chip to facilitate code execution without any external discrete
ROM device requirements. The program memory can be pro-
grammed using conventional third party memory programmers.
This array can also be programmed in-circuit, using the serial
download mode provided.
A 640-Byte Flash/EE Data Memory space is also provided on-chip.
This may be used as a general-purpose nonvolatile scratchpad
area. User access to this area is via a group of six SFRs. This space
can be programmed at a byte level, although it must first be erased
in 4-byte pages.
ADuC816 Flash/EE Memory Reliability
The Flash/EE Program and Data Memory arrays on the ADuC816
are fully qualified for two key Flash/EE memory characteristics,
namely Flash/EE Memory Cycling Endurance and Flash/EE
Memory Data Retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many Program, Read, and Erase cycles. In real
terms, a single endurance cycle is composed of four independent,
sequential events. These events are defined as:
a. initial page erase sequence
b. read/verify sequence
A single Flash/EE
c. byte program sequence
Memory
d. second read/verify sequence
Endurance Cycle
In reliability qualification, every byte in both the program and
data Flash/EE memory is cycled from 00 hex to FFhex until a
first fail is recorded signifying the endurance limit of the on-chip
Flash/EE memory.
As indicated in the specification pages of this data sheet, the
ADuC816 Flash/EE Memory Endurance qualification has been
carried out in accordance with JEDEC Specification A117 over
the industrial temperature range of –40
°C, +25°C, and +85°C.
The results allow the specification of a minimum endurance figure
over supply and temperature of 100,000 cycles, with an endurance
figure of 700,000 cycles being typical of operation at 25
°C.
Retention quantifies the ability of the Flash/EE memory to retain
its programmed data over time. Again, the ADuC816 has been
qualified in accordance with the formal JEDEC Retention Life-
time Specification (A117) at a specific junction temperature
(TJ = 55
°C). As part of this qualification procedure, the Flash/EE
memory is cycled to its specified endurance limit described above,
before data retention is characterized. This means that the Flash/
EE memory is guaranteed to retain its data for its full specified
retention lifetime every time the Flash/EE memory is repro-
grammed. It should also be noted that retention lifetime, based
on an activation energy of 0.6 eV, will derate with TJ as shown
in Figure 26.
40
60
70
90
TJ JUNCTION TEMPERATURE – C
RETENTION
–
Years
250
200
150
100
50
0
50
80
110
300
100
ADI SPECIFICATION
100 YEARS MIN.
AT T
J = 55 C
Figure 26. Flash/EE Memory Data Retention
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