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| 型號： | ADUC814BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 49/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 28-TSSOP |
| 標準包裝： | 2,500 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 17 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 6x12b; D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR |
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ADuC814
Rev. A | Page 53 of 72
UART SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit and
receive simultaneously. It is also receive-buffered, meaning it
can begin receiving a second byte before a previously received
byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second
byte is complete, the first byte is lost. The physical interface to
the serial data network is via Pins RxD (P3.0) and TxD (P3.1),
while the SFR interface to the UART is comprised of the
following registers.
SBUF
The serial port receive and transmit registers are both accessed
through the SBUF SFR (SFR address = 99H). Writing to SBUF
loads the transmit register and reading SBUF accesses a
physically separate receive register.
SCON
UART Serial Port Control Register
SFR Address
98H
Power-On Default
00H
Bit Addressable
Yes
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Table 26. SCON SFR Bit Designations
Bit No.
Name
Description
7
SM0
6
SM1
UART Serial Mode Select Bits.
These bits select the serial port operating mode as follows:
SM0
SM1
Selected Operating Mode
0
Mode 0: Shift Register, fixed baud rate (Core_Clk/2)
0
1
Mode 1: 8-bit UART, variable baud rate
1
0
Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or (Core_Clk/32)
1
Mode 3: 9-bit UART, variable baud rate
5
SM2
Multiprocessor Communication Enable Bit.
Enables multiprocessor communication in Modes 2 and 3.
In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI is not activated if a valid stop bit is not received. If SM2 is cleared, RI is set as soon as the byte
of data is received.
In Mode 2 or 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI is set as soon
as the byte of data is received.
4
REN
Serial Port Receive Enable Bit.
Set by the user software to enable serial port reception.
Cleared by the user software to disable serial port reception.
3
TB8
Serial Port Transmit (Bit 9).
The data loaded into TB8 is the ninth data bit that is transmitted in Modes 2 and 3.
2
RB8
Serial port Receiver Bit 9.
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8.
1
TI
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3.
Cleared by the user software.
0
RI
Serial Port Receive Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3.
Cleared by user software.
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