參數(shù)資料
型號(hào): ADUC814BRUZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 28/72頁
文件大?。?/td> 0K
描述: IC MCU 8K FLASH ADC/DAC 28-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 16.78MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 17
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 640 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x12b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 帶卷 (TR)
配用: EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR
ADuC814
Rev. A | Page 34 of 72
USER INTERFACE TO OTHER ON-CHIP ADuC814 PERIPHERALS
This section gives a brief overview of the various peripherals
also available on-chip. A summary of the SFRs used to control
and configure these peripherals is also given.
DACS
The ADuC814 incorporates two 12-bit, voltage output DACs
on-chip. Each DAC has a rail-to-rail voltage output buffer capa-
ble of driving 10 k/100 pF. They have two selectable ranges,
0 V to VREF (an external or the internal band gap 2.5 V
reference) and 0 V to AVDD, and can operate in 12-bit or 8-bit
modes. DAC operation is controlled by a single special function
(SFR) register, DACCON. Each DAC has two data registers,
DACxH/L. The DAC0 and DAC1 outputs share pins with ADC
inputs ADC4 and ADC5, respectively. When both DACs are on,
the number of analog inputs is reduced to four. Note that in
12-bit mode, the DAC voltage output is updated as soon as the
DACL data SFR has been written; therefore, the DAC data
registers should be updated as DACH first, followed by DACL.
When using the DACs on the VREF range it is necessary to power
up the ADC to enable the reference to the DAC section.
See Note 1.
DACCON
DAC Control Register
SFR Address
FDH
Power-On Default
04H
Bit Addressable
No
MODE
RNG1
RNG0
CLR1
CLR0
SYNC
PD1
PD0
Table 12. DACCON SFR Bit Designations
Bit No.
Name
Description
7
MODE
Mode Select Bit. Selects either 12-bit or 8-bit mode for both DACs.
Set to 1 by the user to enable 8-bit mode (DACxL is the active data register).
Set to 0 by the user to enable 12-bit mode.
6
RNG1
DAC1 Output Voltage Range Select Bit.
Set to 1 by the user to configure DAC1 range of 0 V to AVDD.
Set to 0 by the user to configure DAC1 range of 0 V to 2.5 V (VREF range) 1.
5
RNG0
DAC0 Output Voltage Range Select Bit.
Set to 1 by he user to configure DAC0 range of 0 V to AVDD.
Set to 0 by the user to configure DAC0 range of 0 V to 2.5 V (VREF range) 1.
4
CLR1
DAC1 Clear Bit.
Set to 1 by the user to enable normal DAC1 operation.
Set to 0 by the user to force DAC1 output voltage to 0 V.
3
CLR0
DAC0 Clear Bit.
Set to 1 by the user to enable normal DAC0 operation.
Set to 0 by the user to force DAC0 output voltage to 0 V.
2
SYNC
DAC0/1 Update Synchronization Bit.
Set to 1 by the user to enable asynchronous update mode. The DAC outputs update as soon as the DACxL SFRs are
written.
Set to 0 by the user to enable synchronous update mode. The user can simultaneously update both DACs by first
updating the DACxH/L SFRs while SYNC is 0. Both DACs then update simultaneously when the SYNC bit is set to 1.
1
PD1
DAC1 Power-Down Bit.
Set to 1 by the user to power up DAC1.
Set to 0 by the user to power down DAC1.
0
PD0
DAC0 Power-Down Bit.
Set to 1 by the user to power up DAC0.
Set to 0 by the user to power down DAC0.
1For correct DAC operation on the 2.5 V to VREF range, the ADC must be powered on.
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