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參數資料
| 型號： | ADUC814BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 29/72頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 28-TSSOP |
| 標準包裝： | 2,500 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數： | 17 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數據轉換器： | A/D 6x12b; D/A 2x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR |
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ADuC814
Rev. A | Page 35 of 72
DACxH/L
DAC0 and DAC1 Data Registers
Function
DAC Data Registers, written by the user to update the DAC outputs.
SFR Address
DAC0L (DAC0 data low byte) –> F9H DAC0H (DAC0 data high byte) –> FAH;
DAC1L (DAC1 data low byte) –> FBH DAC1H (DAC1 data high byte) –> FCH
Power-On Default
00H –> Both DAC0 and DAC1 data registers.
Bit Addressable
No –> Both DAC0 and DAC1 data registers.
The 12-bit DAC data should be written into DACxH/L right-justified such that DACL contains the lower eight bits, and the lower nibble
of DACH contains the upper four bits.
Using the DACs
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional equivalent
of which is illustrated in Figure 38. Features of this architecture
include inherent guaranteed monotonicity and excellent differ-
ential linearity.
OUTPUT
BUFFER
HIGH Z
DISABLE
(FROM MCU)
DAC0
R
ADuC814
AVDD
VREF
02748-A
-044
Figure 38. Resistor String DAC Functional Equivalent
As illustrated in Figure 38, the reference source for each DAC is
user selectable in software. It can be either AVDD or VREF. In
0 V-to-AVDD mode, the DAC output transfer function spans
from 0 V to the voltage at the AVDD pin. In 0 V-to-VREF mode,
the DAC output transfer function spans from 0 V to the internal
VREF, or if an external reference is applied, the voltage at the VREF
pin. The DAC output buffer features a true rail-to-rail output
stage implementation. This means that, unloaded, each output is
capable of swinging to within less than 100 mV of both AVDD
and ground. Moreover, the DAC’s linearity specification (when
driving a 10 k resistive load to ground) is guaranteed through
the full transfer function except Codes 0 to 48, and, in 0 V-to-
AVDD mode only, Codes 3945 to 4095. Linearity degradation
near ground and VDD is caused by saturation of the output
buffer, and a general representation of its effects (neglecting
offset and gain error) is illustrated in Figure 39. The dotted line
in Figure 39 indicates the ideal transfer function, and the solid
line represents what the transfer function might look like with
endpoint nonlinearities due to saturation of the output buffer.
Note that Figure 39 represents a transfer function in 0 V-to-VDD
mode only. In 0 V-to-VREF mode (with VREF < VDD), the lower
nonlinearity would be similar, but the upper portion of the
transfer function would follow the ideal line right to the end
(VREF in this case, not VDD), showing no signs of upper endpoint
linearity error.
VDD
VDD–50mV
50mV
0mV
VDD–100mV
100mV
000H
FFFH
02748-A
-045
Figure 39. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in Figure 39
get worse as a function of output loading. Most ADuC814
specifications assume a 10 k resistive load to ground at the
DAC output. As the output is forced to source or sink more
current, the nonlinear regions at the top or bottom (respectively)
of Figure 39 become larger. With larger current demands, this
can significantly limit output voltage swing. Figure 40 and
Figure 41 illustrate this behavior. Note that the upper trace in
each of these figures is valid only for an output range selection
of 0 V-to-AVDD. In 0 V-to-VREF mode, DAC loading does not
cause high-side voltage drops as long as the reference voltage
remains below the upper trace in the corresponding figure. For
example, if AVDD = 3 V and VREF = 2.5 V, the high-side voltage is
not affected by loads less than 5 mA. But around 7 mA, the
that at these higher currents the output cannot reach VREF.
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| ADUC814BRUZ-REEL7 | 功能描述:IC MCU 8K FLASH ADC/DAC 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設備:欠壓檢測/復位，LED，POR，PWM，WDT 輸入/輸出數:16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數據轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| ADUC816 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ADuC816: MicroConverter?= Dual 16-Bit ADC + 12-Bit DAC + Flash MCU Data Sheet (Rev. 0. 2/01 |
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