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參數(shù)資料
| 型號： | ADUC814BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/72頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 28-TSSOP |
| 標準包裝： | 2,500 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 17 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 6x12b; D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR |
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ADuC814
Rev. A | Page 29 of 72
gain coefficient compensates for a larger analog input signal
range and scales down the ADC transfer function, effectively
decreasing the slope of the transfer function. The maximum
analog input signal range for which the gain coefficient can
compensate is 1.035 × VREF, and the minimum input range is
0.965 × VREF, which equates to typically ±3.5% of the reference
voltage.
CALIBRATING THE ADC
The ADuC814 has two hardware calibration modes, device
calibration and system calibration, that can be easily initiated by
the user software. The ADCCON3 SFR is used to calibrate the
ADC. See Table 8.
Device calibration is so called because the relevant signals used
for the calibration are available internally to the ADC. This
calibration method can be used to compensate for significant
changes in operating conditions, such as core frequency, analog
input range, reference voltage and supply voltages. In this
calibration mode, offset calibration uses internal AGND
selected via the ADCCON2 register bits CS3–CS0 (1011), and
gain calibration uses internal VREF selected by CS3–CS0 (1100).
Offset calibration should be executed first, followed by gain
calibration.
System calibration is so called because the AGND and VREF
required for calibration must be the system AGND and VREF
signals. These must be supplied in turn, externally, to the ADC
inputs. This calibration method can be used to compensate for
both internal and external system errors. To perform system
calibration using an external reference, tie system ground and
reference to any two of the six selectable inputs. Enable external
reference mode (ADCCON1.6). Select the channel connected to
AGND via CS3–CS0 and perform system offset calibration.
Select the channel connected to VREF via CS3–CS0 and perform
system gain calibration.
INITIATING CALIBRATION IN CODE
When calibrating the ADC, ADCCON1 should be set to the
configuration in which the ADC is used. The ADCCON3
register can then be used to configure and execute the offset
and gain calibration required in sequence.
Configure the ADC as required. In this case, ADCCLK = /4,
acquisition time is set to 1 clock (TACQ), and ADC is enabled.
MOV ADCCON1,#0D0H
;ADC on, ADCCLK set to
;divide by 4, 1 acquisition
;clock (Tacq)
To perform device offset calibration:
MOV ADCCON2,#0BH
;select internal AGND
MOV ADCCON3,#25H
;select offset calibration,
;31 averages per bit,
;offset calibration
To perform device gain calibration:
MOV ADCCON2,#0CH
;select internal VREF MOV
ADCCON3,#27H
;select offset calibration,
;31 averages per bit,
;offset calibration
To perform system offset calibration:
Connect system AGND to an ADC input (Channel 0 in this case).
MOV ADCCON2,#00H
;select external AGND
MOV ADCCON3,#25H
;select offset calibration,
;31 averages per bit
To perform system gain calibration:
Connect system VREF to an ADC input (Channel 1 in this case).
MOV ADCCON2,#01H
;select external VREF MOV
ADCCON3,#27H
;select offset calibration,
;31 averages / bit (NUMAV),
;offset calibration
The calibration cycle time TCAL is calculated by
TCAL = 14 × ADCCLK × NUMAV × (16 + TACQ)
For an ADCCLK/FCORE, divide ratio of 4, a TACQ = 1 ADCCLK,
NUMAV = 31, the calibration cycle time is
TCAL = 14 × (1 / 4194304) × 31 × (16 + 1)
TCAL = 1.76 mS
In a calibration cycle, the ADC busy flag (Bit 7), instead of
framing an individual ADC conversion as in normal mode, goes
high at the start of calibration and returns to zero only at the
end of the calibration cycle. It can therefore be monitored in
code to indicate when the calibration cycle is completed. The
following code can be used to monitor the BUSY signal during
a calibration cycle.
WAIT:
MOV A, ADCCON3
;move ADCCON3 to A
JB ACC.7, WAIT
;If bit 7 is set jump to
WAIT
;else continue
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