參數(shù)資料
型號(hào): ADUC814BRUZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 53/72頁
文件大小: 0K
描述: IC MCU 8K FLASH ADC/DAC 28-TSSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 16.78MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 17
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x12b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 帶卷 (TR)
配用: EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR
ADuC814
Rev. A | Page 57 of 72
INTERRUPT SYSTEM
The ADuC814 provides a total of twelve interrupt sources with two priority levels. The control and configuration of the interrupt system
is carried out through three interrupt-related SFRs.
IE
Interrupt Enable Register
IP
Interrupt Priority Register
IEIP2
Secondary Interrupt Enable and Priority Register
IE
Interrupt Enable Register
SFR Address
A8H
Power-On Default
00H
Bit Addressable
Yes
EA
EADC
ET2
ES
ET1
EX1
ET0
EX0
Table 29. IE SFR Bit Designations
Bit No.
Name
Description
7
EA
Global Interrupt Enable.
Set by the user to enable all interrupt sources.
Cleared by the user to disable all interrupt sources.
6
EADC
ADC Interrupt.
Set by the user to enable the ADC interrupt.
Cleared by the user to disable the ADC interrupt.
5
ET2
Timer 2 Interrupt.
Set by the user to enable the Timer 2 interrupt.
Cleared by the user to disable the Timer 2 interrupt.
4
ES
UART Serial Port Interrupt.
Set by the user to enable the UART serial port interrupt.
Cleared by the user to disable the UART serial port interrupt.
3
ET1
Timer 1 Interrupt.
Set by the user to enable the Timer 1 interrupt.
Cleared by the user to disable the Timer 1 interrupt.
2
EX1
INT1 Interrupt.
Set by the user to enable the External Interrupt 1.
Cleared by the user to disable the External Interrupt 1.
1
ET0
Timer 0 Interrupt.
Set by the user to enable the Timer 0 interrupt.
Cleared by the user to disable the Timer 0 interrupt.
0
EX0
INT0 Interrupt.
Set by the user to enable the External Interrupt 0.
Cleared by the user to disable the External Interrupt 0.
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