I2C COMPATIBLE INTERFACE The ADuC814 supports a 2" />
參數(shù)資料
型號： ADUC814BRUZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 41/72頁
文件大?。?/td> 0K
描述： IC MCU 8K FLASH ADC/DAC 28-TSSOP
標(biāo)準(zhǔn)包裝： 1,000
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 17
程序存儲器容量： 8KB（8K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
包裝： 帶卷 (TR)
配用： EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR
ADuC814
Rev. A | Page 46 of 72
I2C COMPATIBLE INTERFACE
The ADuC814 supports a 2-wire serial interface mode that is
I2C compatible. The I2C compatible interface shares its pins with
the on-chip SPI interface, and therefore the user can enable only
one interface or the other at any given time (see the SPE bit in
SPICON SFR, Table 18). Application Note uC001 describes the
operation of this interface as implemented, and is available on
the MicroConverter website at www.analog.com/microconverter.
This interface can be configured as a software master or hard-
ware slave, and uses two pins in the interface.
SDATA
(Pin 24)
Serial Data I/O
SCLOCK
(Pin 25)
Serial Clock
Three SFRs are used to control the I2C compatible interface.
I2CCON
I2C Control Register
SFR Address
E8H
Power-On Default
00H
Bit Addressable
Yes
MDO
MDE
MCO
MDI
I2CM
I2CRS
I2CTX
I2CI
Table 19. I2CCON SFR Bit Designations
Bit No.
Name
Description
7
MDO
I2C Software Master Data Output Bit (Master Mode Only).
This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit is output on
the SDATA pin if the data output enable (MDE) bit is set.
6
MDE
I2C Software Master Data Output Enable Bit (Master Mode Only).
Set by the user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable SDATA pin as an input (Rx).
5
MCO
I2C Software Master Clock Output Bit (Master Mode Only).
This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit is output on
the SCLOCK pin.
4
MDI
I2C Software Master Data Input Bit (Master Mode Only).
This data bit is used to implement a master I2C receiver interface in software. Data on the SDATA pin is latched into
this bit on SCLOCK if the data output enable (MDE) bit is 0.
3
I2CM
I2C Master/Slave Mode Bit.
Set by the user to enable I2C software master mode.
Cleared by the user to enable I2C hardware slave mode.
2
I2CRS
I2C Reset Bit (Slave Mode Only).
Set by the user to reset the I2C interface.
Cleared by the user code for normal I2C operation.
1
I2CTX
I2C Direction Transfer Bit (Slave Mode Only).
Set by the MicroConverter if the interface is transmitting.
Cleared by the MicroConverter if the interface is receiving.
0
I2CI
I2C Interrupt Bit (Slave Mode Only).
Set by the MicroConverter after a byte has been transmitted or received.
Cleared automatically when user code reads the I2CDAT SFR (see the I2CDAT SFR description that follows).
I2CADD
I2C Address Register
Function
Holds the I2C peripheral address for the part. It may be overwritten by the user code. Application Note uC001 at
www.analog.com/microconverter describes the format of the 7-bit address in detail.
SFR Address
9BH
Power-On Default
55H
Bit Addressable
No
I2CDAT
I2C Data Register
Function
The I2CDAT SFR is written to by the user code to transmit data over the I2C interface, or it is read by the user
code to read data just received via the I2C interface. Accessing the I2CDAT register automatically clears any
pending I2C interrupts and the I2CI bit in the I2CCON SFR.
SFR Address
9AH
Power-On Default
00H
Bit Addressable
No
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