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| 型號： | ADUC814BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/72頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 28-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 17 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 6x12b; D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR |
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ADuC814
Rev. A | Page 27 of 72
Both the ADCCLK frequency and the acquisition time are used
in determining the ADC conversion time. Two other parameters
are also used in this calculation. To convert the acquired signal
into its corresponding digital output word takes 15 ADCCLK
periods (TCONV). When a conversion is initiated, the start of
conversion signal is synchronized to the ADCCLK. This synchro-
nization (TSYNC) can take from 0.5 to 1.5 ADCCLKs to occur.
The total ADC conversion time TADC is calculated using the
following formula:
TADC = TSYNC + TACQ + TCONV
Assuming TSYNC = 1, TACQ = 1 and FCORE/ADCCLK divider of 4.
The total conversion time is calculated by
TADC = (1 + 1 + 15) × (1 / 4194304)
TADC = 4.05 s
These settings allow a maximum conversion speed or sampling
rate of 246.7 kHz.
When converting on the temperature monitor channel, the
conversion time is not controlled via the ADCCON registers. It
is controlled in hardware and sets the ADCCLK to FCORE /32
and uses four acquisition clocks, giving a total ADC conversion
time of
TADC = (1 + 4 + 15) × (1 / 524288) = 38.14 s
Increasing the conversion time on the temperature monitor
channel improves the accuracy of the reading. To further
improve the accuracy, an external reference with low tempera-
ture drift should also be used.
INITIATING ADC CONVERSIONS
After the ADC has been turned on and configured, there are
four methods of initiating ADC conversions.
Single conversions can be initiated in software by setting the
SCONV bit in the ADCCON2 register via user code. This
causes the ADC to perform a single conversion and puts the
result into the ADCDATAH/L SFRs. The SCONV bit is cleared
as soon as the ADCDATA SFRs have been updated.
Continuous conversion mode can be initiated by setting the
CCONV bit in ADCCON2 via user code. This performs back-
to-back conversions at the configured rate (246.7 kHz for the
settings detailed previously). In continuous mode, the ADC
results must be read from the ADCDATA SFRs before the next
conversion is completed to avoid loss of data. Continuous mode
can be stopped by clearing the CCONV bit.
An external signal can also be used to initiate ADC conversions.
Setting Bit 0 in ADCCON1 enables the logic to allow an
external start-of-conversion signal on Pin 7 (CONVST). This
active low pulse should be at least 100 ns wide. The rising edge
of this signal initiates the conversion.
Timer 2 can also be used to initiate conversions. Setting Bit 1
of ADCCON1 enables the Timer 2 overflow signal to start a
conversion. For Timer 2 configuration information, see the
Timers/Counters section.
For both external CONVST and Timer 2 overflow, the conver-
sion rate must be equal to or greater than the conversion time
(TADC) to avoid incorrect ADC results.
When initiating conversions, the user must ensure that only one
of the trigger modes is active at any one time. Initiating conver-
sions with more than one of the trigger modes active results in
erratic ADC behavior.
ADC HIGH SPEED DATA CAPTURE MODE
The on-chip ADC has been designed to run at a maximum
conversion speed of 4.05 s (247 kHz sampling rate). When
converting at this rate, the ADuC814 MCU has 4.05 s to read
the ADC result and store it in memory for further post
processing; otherwise the next ADC sample could be lost. The
time to complete a conversion and store the ADC results
without errors is known as the throughput rate. In an interrupt
driven routine, the MCU also has to jump to the ADC interrupt
service routine, which decreases the throughput rate of the
ADuC814. In applications where the ADuC814 standard
operating mode throughput is not fast enough, an ADC high
speed data capture (HSDC) mode is provided.
In HSDC mode, ADC results are transferred to the SPI logic
without intervention from the ADuC814 core logic. In applica-
tions where the ADC throughput is slow, the HSDC logic operates
in non-pipelined mode (Figure 29). In this mode, there is
adequate time for the ADC conversion and the ADC-to-SPI
data transfer to complete before the next start of conversion. As
the ADC throughput increases, the HSDC logic begins to operate
in pipelined mode as shown in Figure 30.
ADCDATAH
ADCDATAL
MOSI
SCLOCK
BUSY
CONVST
02748-A
-036
Figure 29. High Speed Data Capture Logic Timing (Non-Pipelined Mode)
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