參數資料
型號: ADUC814BRUZ-REEL7
廠商: Analog Devices Inc
文件頁數: 47/72頁
文件大?。?/td> 0K
描述: IC MCU 8K FLASH ADC/DAC 28-TSSOP
標準包裝: 1,000
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 16.78MHz
連通性: I²C,SPI,UART/USART
外圍設備: POR,PSM,溫度傳感器,WDT
輸入/輸出數: 17
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 640 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數據轉換器: A/D 6x12b; D/A 2x12b
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 帶卷 (TR)
配用: EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR
ADuC814
Rev. A | Page 51 of 72
T2CON
Timer/Counter 2 Control Register
SFR Address
C8H
Power-On Default
00H
Bit Addressable
Yes
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CNT2
CAP2
Table 24. T2CON SFR Bit Designations
Bit No.
Name
Description
7
TF2
Timer 2 Overflow Flag.
Set by hardware on a Timer 2 overflow. TF2 is not set when either RCLK or TCLK = 1.
Cleared by the user software.
6
EXF2
Timer 2 External Flag.
Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
Cleared by the user software.
5
RCLK
Receive Clock Enable.
Set by the user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port in Modes 1 and 3.
Cleared by the user to enable Timer 1 overflow to be used for the receive clock.
4
TCLK
Transmit Clock Enable Bit.
Set by the user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3.
Cleared by the user to enable Timer 1 overflow to be used for the transmit clock.
3
EXEN2
Timer 2 External Enable Flag.
Set by the user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being
used to clock the serial port.
Cleared by the user for Timer 2 to ignore events at T2EX.
2
TR2
Timer 2 Start/Stop Control Bit.
Set by the user to start Timer 2.
Cleared by the user to stop Timer 2.
1
CNT2
Timer 2 timer or counter function select bit.
Set by the user to select counter function (input from external T2 pin).
Cleared by the user to select timer function (input from on-chip core clock).
0
CAP2
Timer 2 Capture/Reload Select Bit.
Set by the user to enable captures on negative transitions at T2EX if EXEN2 = 1.
Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1.
When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow.
Timer/Counter 2 Data Registers
Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and timer
capture/reload registers.
TH2 and TL2
Timer 2, data high byte and low byte.
SFR Address
CDH, CCH, respectively
RCAP2H and RCAP2L
Timer 2, Capture/Reload byte and low byte.
SFR Address
CBH, CAH, respectively
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