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| 型號： | ADUC7128BCPZ126 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 63/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 64-LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，POR，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 28 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 64-LFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
| 配用： | EVAL-ADUC7128QSPZ-ND - KIT DEV FOR ADUC7128 |
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ADuC7128/ADuC7129
Rev. 0 | Page 66 of 92
I2CxSSTA Register
Name
Address
Default Value
Access
I2C0SSTA
0xFFFF0804
0x01
R
I2C1SSTA
0xFFFF0904
0x01
R
I2CxSSTA is a status register for the slave channel.
Table 93. I2CxSSTA MMR Bit Designations
Bit
Value
Description
31:15
Reserved. These bits should be written as 0.
14
START Decode Bit.
Set by hardware if the device receives a valid start and matching address.
Cleared by an I2C stop condition or an I2C general call reset.
13
Repeated START Decode Bit.
Set by hardware if the device receives a valid repeated start and matching address.
Cleared by an I2C stop condition, a read of the I2CxSSTA register, or an I2C general call reset.
12:11
ID Decode Bits.
00
Received Address Matched ID Register 0.
01
Received Address Matched ID Register 1.
10
Received Address Matched ID Register 2.
11
Received Address Matched ID Register 3.
10
Stop After Start And Matching Address Interrupt.
Set by hardware if the slave device receives an I2C STOP condition after a previous I2C START condition
and matching address.
Cleared by a read of the I2CxSSTA register.
9:8
General Call ID.
00
No General Call.
01
General Call Reset and Program Address.
10
General Call Program Address.
11
General Call Matching Alternative ID.
7
General Call Interrupt.
Set if the slave device receives a general call of any type.
Cleared by setting Bit 8 of the I2CxCFG register. If it is a general call reset, all registers are at their default
values. If it is a hardware general call, the Rx FIFO holds the second byte of the general call. This is similar
to the I2C0ALT register (unless it is a general call to reprogram the device address). For more details, see
the I2C Bus Specification, Version 2.1, Jan. 2000.
6
Slave Busy.
Set automatically if the slave is busy.
Cleared automatically.
5
No Acknowledge.
Set if master asks for data and no data is available.
Cleared automatically by reading the I2C0SSTA register.
4
Slave Receive FIFO Overflow.
Set automatically if the slave receive FIFO is overflowing.
Cleared automatically by reading I2C0SRX register.
3
Slave Receive IRQ.
Set after receiving data.
Cleared automatically by reading the I2C0SRX register or flushing the FIFO.
2
Slave Transmit IRQ.
Set at the end of a transmission.
Cleared automatically by writing to the I2C0STX register.
1
Slave Transmit FIFO Underflow.
Set automatically if the slave transmit FIFO is underflowing.
Cleared automatically by writing to the I2C0STX register.
0
Slave Transmit FIFO Empty.
Set automatically if the slave transmit FIFO is empty.
Cleared automatically by writing twice to the I2C0STX register.
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