VOLTAGE INPUT (VIN+–V<" />
參數(shù)資料
型號(hào)： ADUC7128BCPZ126
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/92頁(yè)
文件大?。?/td> 0K
描述： IC DAS MCU ARM7 ADC/DDS 64-LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： PLA，POR，PWM，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 28
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b; D/A 1x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 64-LFQFN 裸露焊盤(pán)，CSP
包裝： 托盤(pán)
配用： EVAL-ADUC7128QSPZ-ND - KIT DEV FOR ADUC7128
ADuC7128/ADuC7129
Rev. 0 | Page 33 of 92
O
U
T
P
UT
CO
DE
VOLTAGE INPUT (VIN+–VIN–)
0 1111 1111 1110
0 1111 1111 1100
0 1111 1111 1010
0 0000 0000 0001
0 0000 0000 0000
1 1111 1111 1110
1 0000 0000 0100
1 0000 0000 0010
1 0000 0000 0000
–VREF +1LSB
+VREF –1LSB
0LSB
1LSB =
2× VREF
4096
SIGN
BIT
06
02
0-
0
30
Current Consumption
The ADC in standby mode, that is, powered up but not
converting, typically consumes 640 μA. The internal reference
adds 140 μA. During conversion, the extra current is 0.3 μA,
multiplied by the sampling frequency (in kHz).
Timing
Figure 36 gives details of the ADC timing. Users control the
ADC clock speed and the number of acquisition clock in the
ADCCON MMR. By default, the acquisition time is eight clocks
and the clock divider is two. The number of extra clocks (such
as bit trial or write) is set to 19, giving a sampling rate of 774 kSPS.
For conversion on the temperature sensor, the ADC acquisition
time is automatically set to 16 clocks and the ADC clock divider
is set to 32. When using multiple channels, including the
temperature sensor, the timing settings revert back to the user-
defined settings after reading the temperature sensor channel.
Figure 34. ADC Transfer Function in Differential Mode
TYPICAL OPERATION
Once configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides
an 11-bit result in the ADC data register.
ADC CLOCK
ACQ
BIT TRIAL
DATA
ADCSTA = 0
ADCSTA = 1
ADC INTERRUPT
WRITE
CONVSTART
ADCBUSY
ADCDAT
06
020-
032
The top four bits are the sign bits, and the 12-bit result is placed
from Bit 16 to Bit 27, as shown in Figure 35. For fully differential
mode, the result is ±11 bits. Again, it should be noted that in
fully differential mode, the result is represented in twos comple-
ment format shifted one bit to the right, and in pseudo differential
and single-ended mode, the result is represented in straight
binary format.
SIGN BITS
12-BIT ADC RESULT
3127
16 15
0
06
02
0
-03
1
Figure 35. ADC Result Format
Figure 36. ADC Timing
ADC MMRs Interface
The ADC is controlled and configured via a number of MMRs (see Table 32) that are described in detail in the following pages.
Table 32. ADC MMRs
Name
Description
ADCCON
ADC Control Register. Allows the programmer to enable the ADC peripheral, to select the mode of operation of the ADC (either
single-ended, pseudo differential, or fully differential mode), and to select the conversion type (see Table 33).
ADCCP
ADC Positive Channel Selection Register.
ADCCN
ADC Negative Channel Selection Register.
ADCSTA
ADC Status Register. Indicates when an ADC conversion result is ready. The ADCSTA register contains only one bit, ADCREADY
(Bit 0), representing the status of the ADC. This bit is set at the end of an ADC conversion generating an ADC interrupt. It is
cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be
read externally via the ADCBusy pin. This pin is high during a conversion. When the conversion is finished, ADCBusy goes back low.
This information can be available on P0.5 (see the General-Purpose I/O section) if enabled in the GP0CON register.
ADCDAT
ADC Data Result Register. Holds the 12-bit ADC result, as shown in Table 35.
ADCRST
ADC Reset Register. Resets all the ADC registers to their default values.
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