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| 型號(hào)： | ADUC7128BCPZ126 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 62/92頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 64-LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，POR，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 28 |
| 程序存儲(chǔ)器容量： | 126KB（63K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 64-LFQFN 裸露焊盤(pán)，CSP |
| 包裝： | 托盤(pán) |
| 配用： | EVAL-ADUC7128QSPZ-ND - KIT DEV FOR ADUC7128 |
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ADuC7128/ADuC7129
Rev. 0 | Page 65 of 92
I2C-COMPATIBLE INTERFACES
The ADuC7128/ADuC7129 support two fully licensed I2C
interfaces. The I2C interfaces are both implemented as full
hardware master and slave interfaces. Because the two I2C
interfaces are identical, only I2C0 is described in detail. Note
that the two masters and slaves have individual interrupts.
Note that when configured as an I2C master device, the
ADuC7128/ADuC7129 cannot generate a repeated start
condition.
The two pins used for data transfer, SDA and SCL, are configured
in a wire-AND’ed format that allows arbitration in a multimaster
system. These pins require external pull-up resistors. Typical
pull-up values are 10 kΩ.
The I2C bus peripheral addresses in the I2C bus system are
programmed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I2C system consists of a master
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the address of the slave
device and the direction of the data transfer in the initial
address transfer. If the master does not lose arbitration and the
slave acknowledges, then the data transfer is initiated. This
continues until the master issues a stop condition and the bus
becomes idle.
The I2C peripheral master and slave functionality are
independent and can be simultaneously active. A slave is
activated when a transfer has been initiated on the bus.
If it is not addressed, it remains inactive until another transfer is
initiated. This also allows a master device, which has lost
arbitration, to respond as a slave in the same cycle.
Serial Clock Generation
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2C0DIV MMR as follows:
)
(2
)
2
(
DIVL
DIVH
+
=
UCLK
CLOCK
ERIAL
S
f
where:
fUCLK is the clock before the clock divider.
DIVH is the high period of the clock.
DIVL is the low period of the clock.
Thus, for 100 kHz operation
DIVH = DIVL = 0xCF
and for 400 kHz
DIVH = 0x28 DIVL = 0x3C.
The I2CxDIV register corresponds to DIVH:DIVL.
Slave Addresses
Register I2C0ID0, Register I2C0ID1, Register I2C0ID2, and
Register I2C0ID3 contain the device IDs. The device compares
the four I2C0IDx registers to the address byte. The seven most
significant bits of either ID register must be identical to that of
the seven most significant bits of the first address byte received
to be correctly addressed. The LSB of the ID registers, transfer
direction bit, is ignored in the process of address recognition.
I2C REGISTERS
The I2C peripheral interface consists of 18 MMRs that are
discussed in this section.
I2CxMSTA Register
Name
Address
Default Value
Access
I2C0MSTA
0xFFFF0800
0x00
R
I2C1MSTA
0xFFFF0900
0x00
R
I2CxMSTA is a status register for the master channel.
Table 92. I2C0MSTA MMR Bit Designations
Bit
Description
7
Master Transmit FIFO Flush.
Set by user to flush the master Tx FIFO.
Cleared automatically once the master Tx FIFO is flushed.
This bit also flushes the slave receive FIFO.
6
Master Busy.
Set automatically if the master is busy.
Cleared automatically.
5
Arbitration Loss.
Set in multimaster mode if another master has the bus.
Cleared when the bus becomes available.
4
No Acknowledge.
Set automatically if there is no acknowledge of the
address by the slave device.
Cleared automatically by reading the I2C0MSTA register.
3
Master Receive IRQ.
Set after receiving data.
Cleared automatically by reading the I2C0MRX register.
2
Master Transmit IRQ.
Set at the end of a transmission.
Cleared automatically by writing to the I2C0MTX register.
1
Master Transmit FIFO Underflow.
Set automatically if the master transmit FIFO is
underflowing.
Cleared automatically by writing to the I2C0MTX register.
0
Master TX FIFO Not Full.
Set automatically if the slave transmit FIFO is not full.
Cleared automatically by writing twice to the I2C0STX
register.
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